
Chapter 3
DDR SDRAM Interface
183
24081D—February 2002
AMD-761™ System Controller Software/BIOS Design Guide
Preliminary Information
Note:
The AMD-761 system controller provides differential clocks,
CLKOUTH and CLKOUTL, for the DDR DIMMs. This single
CLKOUT drive strength and slew setting applies for both
polarities of CLKOUT.
Device Chip Select (CS[7:0]#)
Command bus A (RASA#, CASA#, WEA#, and CKEA#)
Command bus B (RASB#, CASB#, WEB#, and CKEB#)
Memory address bus A (MAA[14:0])
Memory address bus B (MAB[14:0])
Signal integrity studies have shown that P and N slew settings
of 101b and a P drive strength setting of 11b and an N drive
strength setting of 10b for
all
of the signal groups specified
above provide adequate edge rates across various unbuffered
and registered DIMM devices and population. A proper drive
strength and slew setting for (Dev 0:F1:0x8C, bits [31:0]) is
0E_2D_0E_2Dh.