Chapter 3
DDR SDRAM Interface
167
24081D—February 2002
AMD-761™ System Controller Software/BIOS Design Guide
Preliminary Information
over the application of the Load Mode Register command and
the Load Mode Register command is the last command applied
in the DDR initialization, this bit can be polled to prove status
as to when the entire DDR initialization is complete.
Suspend to Ram
Control
The Suspend to RAM bits (Dev 0:F0:0x58, bits [22:21]) are used
by BIOS to communicate the power-up sequence to the
AMD-761 system controller.
The BIOS usage of the Suspend to RAM control bits are
defined in the power management section (see Section 4.4.1 on
page 191).
Burst Refresh Enable
The Burst Refresh bit (Dev 0:F0:0x58, bit [20]) allows the
AMD-761 system controller to skip refreshes that are queued,
until the maximum number (four) is reached.
Burst refresh support is a performance enhancement that
prevents refresh requests from interfering with memory
requests. Refresh requests that would have interfered with
memory requests would normally stall the memory accesses or
interfere with the open page policy by prematurely closing
pages due to the refresh. When burst refresh is enabled and the
burst queue is beginning to fill up, the DRAM controller treats
the refresh queue requests as an urgent priority.
Refresh Disable
The Refresh Disable bit (Dev 0:F0:0x58, bit [19]) allows the
disabling of refresh cycles for debug purposes only. This bit is
not reset during a system reset and it is therefore the
responsibility of BIOS to write this bit to a 0 to enable
refresh cycles.
Cycles per Refresh
The Cycles per Refresh bits (Dev 0:F0:0x58, bits [17:16])
provide a setting to specify the DDR refresh rate. The refresh
rate is tied directly to the clock frequency, thus it is important
for BIOS to configure the refresh rate based on the AMD-761
system controller frequency. BIOS should first determine the
AMD-761 system controller operating frequency by reading
(Dev 0:F0:0x58, bits [21:20]) and setting these bits according to
Table 28 below. The refresh rate should not be configured
slower than that specified by any of the DDR devices installed.
( E a ch D I M M i n s t a l l e d m ay h ave a d i f f e re n t re f re s h
requirement, so it is important to choose the refresh rate that
satisfies the least common denominator for all DIMMs.)