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AMD-761™ System Controller Programmer’s Interface
Chapter 2
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Preliminary Information
DDR PDL Configuration Registers
Register Description
These registers allow configuration of programmable delay lines 0–17. There are a total of 18 PDLs (one per DDR DQS pin in
x4 mode). Note that these registers are not initialized at reset time, but must be initialized by BIOS for proper operation. This
action should be done prior to attempting DRAM access, and a software initiated calibration should be forced.
31
30
29
28
27
26
25
24
Bit
Clk_Dly
Reset
X
X
X
X
X
X
X
X
R/W
R
23
22
21
20
19
18
17
16
Bit
SW_Cal_Dly
Reset
X
X
X
X
X
X
X
X
R/W
R/W
15
14
13
12
11
10
9
8
Bit
Cal_Dly
Reset
X
X
X
X
X
X
X
X
R/W
R
7
6
5
4
3
2
1
0
Bit
Act_Dly
Reset
X
X
X
X
X
X
X
X
R/W
R/W