AMCI SD4840EK, Руководство пользователя

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TASK 4 (
OPTIONAL
)
D
ISTRIBUTED
C
LOCK
- SYNC0 S
ETUP
By default, the SD4840EK acts on the data from the EtherCAT master as soon as it is transmitted to the
device. This mode of operation is called “SM-Synchron”. The data transfer is synchronized with the Sync-
Manager 2 event. This synchronization is more than adequate for most machine types.
On very high speed machines, or large machines that require more than one EtherCAT transfer to update all of
the I/O, it may be necessary to use the EtherCAT Distributed Clock mechanism to synchronize the start of
moves with other motion axes or other devices on the EtherCAT network.
Using the Distributed Clock feature adds complexity to the system that may not be needed. On large
machines that require more than one EtherCAT transfer to update all of the I/O, configure the network to
update all of the axes with one transfer. This may eliminate the need to use the DC functionality on large
machines.
4.1 Verify Main PLC Task Timing
1) In the
Solutions Explorer
, expand out
System

Tasks
so that the tasks are visible. Double click on the task
assigned to the main PLC. This task is typically named
PlcTask
. In the windows that open, note the value
for Cycle Ticks and its time in milliseconds. These values are typically 10 ticks and 10.000 milliseconds.

You can change the timing of the main task here, but this will affect the timing of every program that
runs under this task.
Table T4.1 Main PLC Task Timing
2) If this value is between 2 and 50 milliseconds and the correct update time for the SD4840EK, skip to step
4.3. When setting the
SYNC 0 -> Sync Unit Cycle
multiplier in step 6 of 4.3, use a value of 1.
3) If the timing in step 1 above is not correct for the SD4840EK, but the correct time is an integer multiple of
this timing, then skip to step 4.3. When setting the
SYNC 0 -> Sync Unit Cycle
multiplier in step 6 of 4.3,
use the correct integer multiplier.
4) If the timing is step 1 above is not correct for the SD4840EK, and the correct time is
not
an integer multiple
of this timing, then proceed with step 4.2.
This chapter outlines the steps need to configure the SD4840EK to synchronize to
the Sync0 signal from the Distributed Clock (DC) feature instead of the SyncMan-
ager 2 event. This configuration is optional.