IP-48ADM16 HARDWARE REFERENCE MANUAL
ALPHI TECHNOLOGY CORP.
Page 2
REV 1.0
Part Number: 833-13-000-4000
Copyright
©
2007, ALPHI Technology Corporation
Figure 1.1 : Data Flow Block Diagram
1.2 FUNCTIONAL
DESCRIPTION
A data flow block diagram of the
*
is presented in Figure 1-1.
The IP-48ADM16 has 6 fault-protected CMOS analog multiplexers. Each multiplexer
has 8 inputs and one common output. These outputs are acquired by differential
multiplexers. The differential inputs can then be configured for single-ended,
differential, or calibration modes. These outputs go then to a PGA where the gain can
be set for 1, 2, 4, or 8
After the conversion, the data is stored in a 64k by 16 dual ported Data RAM.
Memory pointers can be selected to limit the number of scan gathered, as well as
used to control the generation of interrupts. Continuous acquisition and transfers can
be performed.
Two different threshold levels can be selected for each channel. When enabled the
result of the A/D acquisition is compared with one or both of the thresholds and will
generate a programmable interrupt to the host if the channel is out of the defined
band gap or into the defined band gap.
The board can also be set to monitor one channel and start the acquisition on all the
Channel List whenever the first channel in the channel list is inside or outside a pre-
programmed range.
A programmable digital filter selects the minimum number of consecutive values
before the interrupt is generated, or the acquisition starts.
