IP-48ADM16 HARDWARE REFERENCE MANUAL
ALPHI TECHNOLOGY CORP.
Page 13
REV 1.0
Part Number: 833-13-000-4000
Copyright
©
2007, ALPHI Technology Corporation
3.3.6 Interrupt / DMA source
Address: I 0x0a
When set to “1”, the four lower bits of this register are used to enable interrupt
sources on the IRQ1 line. All the bits of this control registers are set to “0” when the
board is reset.
BIT 03
BIT 02
BIT 01
BIT 00
THRESHOLD INT
SRAM POINTER
SAMPLE AEB
Note
:
The interrupt request is latched, it is necessary to read the Status register to remove
it. This should be done in the interrupt servicing routine.
AEB
When set to “1”, an IRQ1 is generated when the State Machine reaches the end of
the memory as defined in the End Memory Address Pointer.
SAMPLE
When the “SAMPLE” bit is set to “1”, IRQ1 is generated at each start of the scan list.
SRAM POINTER
When set to “1”, an IRQ1 is generated when the State Machine reach a pre-defined
address location located into the DataRAM pointer or a pre-defined number of scan-
list still using the DataRAM pointer pre-programmed with the number of scan (as
selected in the trigger register).
THRESHOLD INTERRUPT
When set to “1”, an IRQ1 is generated, if the threshold detection is enabled and a
Channel List entry has satisfied the conditions to generate the request.
DMA SOURCE
The bits 7 to 4 of this register enable DMA requests. Please note that the signal
DMA-END is not generated by this module.
BIT 07
BIT 06
BIT 05
BIT 04
Reserved Reserved Reserved DATA_AVAILABLE
DATA_AVAILABLE
When this bit is set, every new acquisition data available activates the DMARQ. The
data should be read in the Direct A/D Read register.
