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IP-48ADM16 HARDWARE REFERENCE MANUAL 

ALPHI TECHNOLOGY CORP. 

Page iii 

REV 13 

Part Number: 833-13-000-4000  

Copyright 

©

 2007, ALPHI Technology Corporation 

TABLE OF CONTENTS 

1.

 

GENERAL DESCRIPTION ____________________________________1

 

1.1

 

INTRODUCTION ____________________________________________________ 1

 

1.2

 

FUNCTIONAL DESCRIPTION__________________________________________ 2

 

2.

 

THEORY OF OPERATION ____________________________________3

 

2.1

 

ANALOG INPUTS ___________________________________________________ 3

 

2.1.1

 

S

INGLE

-E

NDED 

M

ODE

__________________________________________________ 4

 

2.1.2

 

D

IFFERENTIAL 

M

ODE

___________________________________________________ 4

 

2.2

 

A/D CONVERTER ___________________________________________________ 5

 

2.2.1

 

A

CQUISITION 

M

ODE

___________________________________________________ 5

 

2.2.2

 

CONTINUOUS

 

MODE ________________________________________________ 6

 

3.

 

INTERFACE TO THE IP CARRIER______________________________7

 

3.1

 

IDSPACE __________________________________________________________ 7

 

3.2

 

MEMSPACE ________________________________________________________ 7

 

3.2.1

 

A

DDRESS 

M

AP

_______________________________________________________ 7

 

3.2.2

 

D

ATA

RAM __________________________________________________________ 8

 

3.2.3

 

C

HANNEL 

L

IST

_______________________________________________________ 8

 

3.2.4

 

T

HRESHOLD 

H

IGH 

RAM _______________________________________________ 10

 

3.2.5

 

T

HRESHOLD 

L

OW 

RAM________________________________________________ 10

 

3.3

 

IOSPACE _________________________________________________________ 11

 

3.3.1

 

A

DDRESS 

M

AP

______________________________________________________ 11

 

3.3.2

 

I

NTERNAL 

C

LOCK 

D

IVISOR 

(ICDH,

 

ICDL) __________________________________ 12

 

3.3.3

 

E

ND 

M

EMORY 

A

DDRESS 

P

OINTER

________________________________________ 12

 

3.3.4

 

S

TATE 

M

ACHINE 

C

URRENT 

A

DDRESS 

P

OINTER

_______________________________ 12

 

3.3.5

 

D

ATA

RAM

 

I

NTERRUPT 

P

OINTER 

R

EGISTER

_________________________________ 12

 

3.3.6

 

I

NTERRUPT 

/

 

DMA

 SOURCE

_____________________________________________ 13

 

3.3.7

 

S

TOP 

A

CQUISITION 

R

EGISTER

___________________________________________ 14

 

3.3.8

 

A

CQUISITION 

C

ONTROL 

R

EGISTER

________________________________________ 14

 

3.3.9

 

T

RIGGER 

R

EGISTER

__________________________________________________ 15

 

3.3.10

 

S

TART 

A

CQUISITION

__________________________________________________ 16

 

3.3.11

 

I

NTERRUPT 

V

ECTOR 

R

EGISTER

__________________________________________ 16

 

3.3.12

 

D

IGITAL 

F

ILTER 

R

EGISTER

______________________________________________ 17

 

3.3.13

 

C

HANNEL 

I

NTERRUPT 

R

EGISTER 

#0

 

[15~0] _________________________________ 17

 

3.3.14

 

C

HANNEL 

I

NTERRUPT 

R

EGISTER 

#1

 

[31~16] ________________________________ 17

 

3.3.15

 

C

HANNEL 

I

NTERRUPT 

R

EGISTER 

#1

 

[47~32] ________________________________ 17

 

3.3.16

 

S

TATUS REGISTER

___________________________________________________ 17

 

3.3.17

 

R

ESET 

I

NTERRUPT 

R

EQUEST 

#0 _________________________________________ 18

 

3.3.18

 

D

IRECT 

A/D

 

R

EAD

___________________________________________________ 18

 

3.4

 

RESET ___________________________________________________________ 18

 

4.

 

CONNECTORS ____________________________________________19

 

5.

 

JUMPER DESCRIPTIONS ___________________________________19

 

5.1

 

CONNECTOR DESCRIPTIONS________________________________________ 20

 

6.

 

APPLICATION EXAMPLE____________________________________21

 

6.1

 

HOW TO SET A CHANNEL AS AD TRIGGER. ___________________________ 21

 

Содержание IP-48ADM16

Страница 1: ...High Density 48 channel 16 bit A D Converter REFERENCE MANUAL 833 13 000 4000 Version 1 3 December 2007 ALPHI TECHNOLOGY CORPORATION 6202 S Maple Avenue 120 Tempe AZ 85283 USA Tel 480 838 2428 Fax 48...

Страница 2: ...n this manual or from the use of information contain herein ALPHI TECHNOLOGY reserves the right to make any changes without notice to this or any of ALPHI TECHNOLOGY s products to improve reliability...

Страница 3: ..._________________________________________ 11 3 3 2 INTERNAL CLOCK DIVISOR ICDH ICDL __________________________________ 12 3 3 3 END MEMORY ADDRESS POINTER ________________________________________ 12 3...

Страница 4: ...13 Part Number 833 13 000 4000 Copyright 2007 ALPHI Technology Corporation 6 2 SINGLE CHANNEL CONVERSION CONTROLLED BY HOST _______________ 21 6 3 SCAN LIST CONVERTED ONCE CONTROLLED BY HOST OR EXTERN...

Страница 5: ...rter Software programmable single ended SE or differential DIFF input and gain for each channel Input Ranges 10V 5V 2 5V 1 25V using a software programmable gain amplifier Additional jumper selectable...

Страница 6: ...stored in a 64k by 16 dual ported Data RAM Memory pointers can be selected to limit the number of scan gathered as well as used to control the generation of interrupts Continuous acquisition and tran...

Страница 7: ...user to have a mix of single ended or differential inputs selected on the fly from the Channel List While a 1 MSPS A D converter convert the selected channel it is possible to select the next channel...

Страница 8: ...in single ended and differential modes IN 40 41 42 43 44 45 46 47 IN 32 33 34 35 36 37 38 39 IN 24 25 26 27 28 29 30 31 OUT MUX 3 A D CONVERTER Gx_00 Gx_01 IN IN PGA MUX 4 MUX 5 MUX 6 IN 8 9 10 11 12...

Страница 9: ...ored Setting the DATARAM pointer to N scan list will store N scan then the DATARAM re start to address zero 3 Next select the trigger source that will start the acquisition Host write to the Start Acq...

Страница 10: ...ure is used Remember that in a real world scenario it is not possible to read the data at the maximum rate that the IP is capable of There is no way to predict the exact performance as it depends on t...

Страница 11: ...ocated in the IP IDENTification Base address These registers are read only ID space address Description Value 01 Ascii I 49 03 Ascii P 50 05 Ascii A 41 07 Ascii C 43 09 Manufacturer identification 99...

Страница 12: ...HOLD HIGH SE DIFF Gain Channel Channel Channel number from 0 to 47 Gain Selection Input gains are selected on a per channel basis according to the following table Gx_7 Gx_6 Gain Selected 0 0 The gain...

Страница 13: ...than Thesh Low 1 1 1 Selected when value is inside the range Table 3 2 2 Threshold Selection SCAN LIST 12X64 IN OUT TH_L TH_H DIFF 0 PGA GAIN CH 47 0 5 0 7 6 8 9 10 11 Bit 63 DATARAM 64Kx16 AEB SCAN...

Страница 14: ...ace 0x020080 The Threshold High RAM is a memory area of 64 12 bit locations mapped within the IP memory space It is used for specifying a threshold high value used by the system to take specific actio...

Страница 15: ...bit 16 23 0x04 R W End Memory Address Pointer 0X06 R State Machine Current Address Pointer 0x08 R W DataRAM Interrupt Pointer register 0x0A R W Interrupt DMA Source 0X0C W Stop Acquisition 0x0E R W A...

Страница 16: ...ivisor low word write 0xd59f 02 ICDH Internal clock divisor high word write 0x04 3 3 3 End Memory Address Pointer Address IOspace 0x04 This content of this register is compared with the State Machine...

Страница 17: ...Address Pointer SAMPLE When the SAMPLE bit is set to 1 IRQ1 is generated at each start of the scan list SRAM POINTER When set to 1 an IRQ1 is generated when the State Machine reach a pre defined addr...

Страница 18: ...when the next entry in the Channel List should be executed Sampling Clock Source Meaning 0 0 Internal Sampling Clock 0 1 Host write to the Start Acquisition Register 1 0 IPSTROBE signal from the IP b...

Страница 19: ...t corresponding to the channel 47 is used as an external EVENT line MASTER This bit when set to 1 will make the IP module the source for the sample clock the signal will be output on IP STROBE signal...

Страница 20: ...tate machine will run as long as the DataRAM pointer is reach or the scan pointer is reach Count Type When set to 0 the DataRAM pointer witch contains an address is compared to the STATE Machine addre...

Страница 21: ...by each channel 15 0 if activated for level threshold detection Each bit can be reset by writing a 1 to the corresponding bit Writing a 0 does not change the state of the bit 3 3 14 Channel Interrupt...

Страница 22: ...ition signal It starts the State machine It is reset in multiple ways IPRESET signal Stop acquisition signal command End pointer DATARAM End SCAN block 3 3 17 Reset Interrupt Request 0 Address IOspace...

Страница 23: ...Programming Header Header for programming Cyclone EP1C12Q240 P2 Factory Use Header used for debugging purpose W1 A D Input settings see page 3 for settings The software programmable PGA allows select...

Страница 24: ...onnection 1 IN00 IN00 26 IN24 IN00 2 IN01 IN01 27 IN25 IN01 3 IN02 IN02 28 IN26 IN02 4 IN03 IN03 29 IN27 IN03 5 IN04 IN04 30 IN28 IN04 6 IN05 IN05 31 IN29 IN05 7 IN06 IN06 32 IN30 IN06 8 IN07 IN07 33...

Страница 25: ...writing at address Start conversion The state machine will continuously convert the selected channel until a threshold_ad signal is generated Then the SM will continue through the scan list 8 A D conv...

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