IP-48ADM16 HARDWARE REFERENCE MANUAL
ALPHI TECHNOLOGY CORP.
Page 17
REV 1.0
Part Number: 833-13-000-4000
Copyright
©
2007, ALPHI Technology Corporation
3.3.12 Digital Filter Register
Address: I 0x16
The 4 lower bits of this 8-bit register select the number of samples that must be in the
threshold interrupt range before actually generating an interrupt. It acts as a digital
filter
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Ad_trig_3 Ad_trig_2 Ad_trig_1 Ad_trig_0 Thres_3 Thres_2 Thres_1 Thres_0
The higher 4 bits of this 8-bit register select the number of time the channel selected
as AD trigger need to be in range before actually starting the acquisition.
3.3.13 Channel Interrupt Register #0 [15~0]
Address: I 0x18
This 16 bit register reflect the status of the interrupt generated by each channel
(15~0) if activated for level threshold detection.
Each bit can be reset by writing a “1” to the corresponding bit. Writing a “0” does not
change the state of the bit.
3.3.14 Channel Interrupt Register #1 [31~16]
Address: I 0x1a
This 16 bit register reflect the status of the interrupt generate by each channel
(31~16) if activated for level threshold detection.
Each bit can be reset by writing a “1” to the corresponding bit. Writing a “0” does not
change the state of the bit.
3.3.15 Channel Interrupt Register #1 [47~32]
Address: I 0x1c
This 16 bit register reflect the status of the interrupt generate by each channel
(47~32) if activated for level threshold detection.
Each bit can be reset by writing a “1” to the corresponding bit. Writing a “0” does not
change the state of the bit.
3.3.16 Status register
Address: I 0x20
BIT 3
BIT 2
BIT 1
BIT 0
Reserved (0)
ACQUIRE_EN
BUSYIN
INTREQ #0
INTREQ #0
This bit shows the state of the interrupt line # 0. Set to “0” when Start acquisition is
generated.
