IP-48ADM16 HARDWARE REFERENCE MANUAL
ALPHI TECHNOLOGY CORP.
Page 11
REV 1.0
Part Number: 833-13-000-4000
Copyright
©
2007, ALPHI Technology Corporation
3.3 IOSPACE
3.3.1 Address Map
The registers are accessed in 16-bit mode. The addresses are as an offset to the
IOspace base address.
I R/W
Register
0x00
R/W
Internal Clock Divisor Low (bit 0-15)
0x02
R/W
Internal Clock Divisor High (bit 16-23)
0x04
R/W
End Memory Address Pointer
0X06
R
State Machine Current Address Pointer
0x08
R/W
DataRAM Interrupt Pointer register
0x0A R/W
Interrupt/DMA
Source
0X0C W Stop
Acquisition
0x0E
R/W
Acquisition Control register
0x10 R/W
Trigger
register
0x12 W Start
Acquisition
0x14
R/W
Interrupt Vector Register
0x16
R/W
Digital Filter Register
0x18
R/W
Channel Interrupt Register #0 (bit 0-15)
0x1A
R/W
Channel Interrupt Register #1 (bit 16-31)
0x1C
R/W
Channel Interrupt Register #2 (bit 32-47)
0x20 R Status
register
0x22
W
Reset Interrupt #0
0x24 R A/D
Register
Table 3.3 IO Registers
