IP-48ADM16 HARDWARE REFERENCE MANUAL
ALPHI TECHNOLOGY CORP.
Page 15
REV 1.0
Part Number: 833-13-000-4000
Copyright
©
2007, ALPHI Technology Corporation
Trigger source
Meaning
0 0
Host write to the Start Acquisition Register
0 1
External Event trigger
1 0
Threshold Logic
3.3.9 Trigger Register
Address: I 0x10
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ENABLE_
THRESH
OLD
Event
Enable
MASTER END_DAT
ARAM
Reserved
(should be
0)
SCAT_SCAN Scan
Block
Count
Type
All the bits are set to “0” upon Reset.
ENABLE_THRESHOLD
When set to “1”, it allows starting an acquisition when a channel designated as
threshold is going in range or out of range.
The Threshold Counter Register defines how many acquisitions have to satisfy the
condition for the acquisition to really start.
Event Enable
When set to “1”, the input corresponding to the channel #47 is used as an external
EVENT line.
MASTER
This bit, when set to 1, will make the IP module the source for the sample clock, the
signal will be output on IP-STROBE signal on the IP bus. The MASTER bit allows the
synchronization of multiple IP’s.
END_DATARAM
This bit specifies what the state machine has to do after reaching the address
indicated in the End Memory Address register. The state machine can:
•
If the bit is set to “0”, reset the state machine address pointer and continue
acquiring data and storing it in the DataRAM.
•
If this bit is set to “1”, the state machine will reset the state machine address
pointer and stop and wait for another start acquisition command.
SCAT_SCAN
When the ENABLE_THRESHOLD bit is set there is 2 behaviors allowed depending
on the state of the SCAT_SCAN bit:
- If “0”, the scan list is activated and acquisition stops only at the end of the
DataRAM memory.
- If “1”, the scan list is activated but stops when the condition that started the
scan disappears.
