Using High-Speed Counter Instructions
12–5
•
Accumulator
≤
Low Preset Bit LP (bit 8) is a reserved bit for all Up
Counters.
For the Bidirectional Counters, if the hardware accumulator becomes less than
or equal to the low preset, the LP bit is set by the controller. If the hardware
accumulator becomes greater than the low preset, the LP bit is reset by the
controller. Do not write to this bit. (Exception – you can set or reset this bit
during the initial configuration of the HSC instruction. See page 12–6 for
more information.)
•
Overflow Caused High-Speed Counter Interrupt Bit IV (bit 7) is set to
identify an overflow as the cause for the execution of the high-speed counter
interrupt routine. The IN, IH, and IL bits are reset by the controller when the IV
bit is set. Examine this bit at the start of the high-speed counter interrupt
routine (file 4) to determine why the interrupt occurred.
•
Underflow caused User Interrupt Bit IN (bit 6) is set to identify an
underflow as the cause for the execution of the high-speed counter interrupt
routine. The IV, IH, and IL bits are reset by the controller when the IN bit is set.
Examine this bit at the start of the high-speed counter interrupt routine (file 4)
to determine why the interrupt occurred.
•
High Preset Reached Caused User Interrupt Bit IH (bit 5) is set to identify
a high preset reached as the cause for the execution of the high-speed counter
interrupt routine. The IV, IN, and IL bits are reset by the controller when the IH
bit is set. Examine this bit at the start of the high-speed counter interrupt
routine (file 4) to determine why the interrupt occurred.
•
Low Preset Reached Caused High-Speed Counter Interrupt Bit IL (bit 4)
is set to identify a low preset reached as the cause for the execution of the
high-speed counter interrupt routine. The IV, IN, and IH bits are reset by the
controller when the IL bit is set. Examine this bit at the start of the high-speed
counter interrupt routine (file 4) to determine why the interrupt occurred.
•
High-Speed Counter Interrupt Pending Bit PE (bit 3) is set to indicate that
a high-speed counter interrupt is waiting for execution. This bit is cleared by
the controller when the high-speed counter interrupt routine begins executing.
This bit is reset if an RAC or RES instruction is executed. Do not write to this
bit.
•
High-Speed Counter Interrupt Lost Bit LS (bit 2) is set if a high-speed
counter interrupt occurs while the PE bit is set. You can reset this bit with an
OTU instruction or by executing an RAC or RES instruction.
•
High-Speed Counter Interrupt Enable Bit IE (bit 1) is set when the
high-speed counter interrupt is enabled to run when a high-speed counter
interrupt condition occurs. It is reset when the interrupt is disabled. This bit is
also set when the high-speed counter is first configured. Do not write to this
bit.
Programming
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