Preface
MicroLogix 1000 Programmable Controllers User Manual
B–12
S:4
Timebase
Status
All 16 bits of this word are assessed by the
controller. The value of this word is zeroed
upon power up in the REM Run mode or entry
into the REM Run or REM Test mode. It is
incremented every 10 ms thereafter.
Application note: You can write any value to
S:4. It will begin incrementing from this value.
You can use any individual bit of this word in
your user program as a 50% duty cycle clock
bit. Clock rates for S:4/0 to S:4/15 are:
20, 40, 80, 160, 320, 640, 1280, 2560, 5120,
10240, 20480, 40960, 81920, 163840, 327680,
and 655360 ms.
The application using the bit must be evaluated
at a rate more than two times faster than the
clock rate of the bit. In the example below, bit
S:4/3 toggles every 80 ms, producing a 160 ms
clock rate. To maintain accuracy of this bit in
your application, the instruction using bit S:4/3
(O:1/0 in this case) must be evaluated at least
once every 79.999 ms
160 ms
S:4/3 cycles in 160 ms
Both S:4/3 and
Output O:1/0 toggle
every 80 ms. O:1/0
must be evaluated
at least once every
79.999 ms.
] [
S:4
3
( )
O:1
0
S:5
Minor Error
Bits
The bits of this word are set by the controller to
indicate that a minor error has occurred in your
ladder program. Minor errors, bits 0 to 7,
revert to major error 0020H if any bit is
detected as being set at the end of the scan.
These bits are automatically cleared on a
power cycle.
S:5/0
Overflow Trap
Dynamic
Configuration
When this bit is set by the controller, it
indicates that a mathematical overflow has
occurred in the ladder program. See S:0/1 for
more information.
If this bit is ever set upon execution of the END
or TND instruction, major error (0020) is
declared. To avoid this type of major error from
occurring, examine the state of this bit
following a math instruction (ADD, SUB, MUL,
DIV, DDV, NEG, SCL, TOD, or FRD), take
appropriate action, and then clear bit S:5/0
using an OTU instruction with S:5/0.
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