Using High-Speed Counter Instructions
12–3
High-Speed Counter Instructions Overview
Use the high-speed counter to detect and store narrow (fast) pulses, and its
specialized instructions to initiate other control operations based on counts reaching
preset values. These control operations include the automatic and immediate
execution of the high-speed counter interrupt routine (file 4) and the immediate
update of outputs based on a source and mask pattern you set.
Counter Data File Elements
The high-speed counter instructions reference counter C5:0. The HSC instruction is
fixed at C5:0. It is comprised of three words. Word 0 is the status word, containing
15 status bits. Word 1 is the preset value. Word 2 is the accumulated value. Once
assigned to the HSC instruction, C5:0 is not available as an address for any other
counter instructions.
CU CD DN OV UN UA HP LP IV IN IH IL PE LS IE
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Preset Value
Accumulator Value
CU = Counter Up Enable Bit
CD = Counter Down Enable Bit
DN = High Preset Reached Bit
OV = Overflow Occurred Bit
UN = Underflow Occurred Bit
UA = Update High-Speed Counter Accumulator Bit
HP = Accumulator
≥
High Preset Bit
LP = Accumulator
≤
Low Preset Bit
IV = Overflow Caused High-Speed Counter Interrupt Bit
IN = Underflow Caused High-Speed Counter Interrupt Bit
IH = High Preset Reached Caused Interrupt Bit
IL = Low Preset Reached Caused Interrupt Bit
PE = High-Speed Counter Interrupt Pending Bit
LS = High-Speed Counter Interrupt Lost Bit
IE = High-Speed Counter Interrupt Enable Bit
Word 0
Word 1
Word 2
Status
Word
Counter preset and accumulated values are stored as signed integers.
Using Status Bits
The high-speed counter status bits are retentive. When the high-speed counter is
first configured, bits 3–7, 14, and 15 are reset and bit 1 (IE) is set.
Programming
efesotomasyon.com - Allen Bradley,Rockwell,plc,servo,drive
