SERIES PMC341 PCI MEZZANINE CARD SIMULTANEOUS ANALOG INPUT MODULE
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ADC Spec’s
Conversion Rate……………….. 125KHz
Input Voltage Range……………
10 Volts
Data Format……………………. Binary 2’s Complement
PMC341
ADC………………………………
Analog Devices AD7894B
ADC Resolution……..…………. 14 Bits
No Missing Codes……………… 14 Bits
Integral Nonlinearity……………
1.5 LSB Maximum
Gain Error
5
………………………
6 LSB Maximum
Bipolar Zero Error
5
…….……..
8 LSB Maximum
Instrumentation Amplifier
INAMP…………………………... Burr-Brown INA128
Nonlinearity………………….…..
0.001% of FSR Maximum
Offset Voltage
5
…………….……
550
Volt Maximum
Gain Error
5
………..………….…
0.024% Maximum
Settling Time…………………. 7
seconds Typical to 0.01%
Note:
5. Software calibration minimizes these error components.
5 Volt Calibration Reference Voltage
Temperature Drift….………….. 2ppm/
C Typical, 5ppm/
C Max.
Maximum Overall Calibrated Error @ 25
C
PMC341 Max. Total Error
6
2.4 LSB
0.014% Span
The maximum corrected (i.e. calibrated) error is the worst case
accuracy. It is the sum of error components due to ADC
quantization of the low and high calibration signals,
instrumentation amplifier, and ADC linearity error at 25
C. For
critical applications multiple input samples should be averaged to
improve performance.
Note:
6. Software calibration must be performed in order to achieve
the specified accuracy. Follow the output connection
recommendations of Chapter 2, to keep non-ideal grounds
from degrading overall system accuracy.
Input Noise
PMC341
7
…………..
1 LSB rms, Typical.
Note:
7. Reference Test Conditions: Temperature 25
C, 125K
conversions/second, using test PC with a 2 meter cable
length connection to the field analog input signal.
External Trigger Input/Output
As An Inpu
t:.....................…..... Must be an active low 5 volt logic
TTL compatible, debounced
signal referenced to digital
common. Conversions are
triggered on the falling edge of
this trigger signal. Minimum pulse
width 250nano seconds.
Conversions are triggered on
channels 0 to 7 within 450nano
seconds of the external trigger
(typically).
As An Output:.......
......…........... Active low 5 volt logic TTL
compatible output is generated.
The trigger pulse is low for
typically 450nano seconds
PCI Local Bus Interface
Compatibility......................…....
.
Conforms to PCI Local Bus
Specification, Revision 2.2 and
PMC Specification,
P1386.1/Draft 2.4
Electrical/Mechanical Interface. Single-Width PMC Module
PCI Target …………………… Implemented by Altera FPGA
4K Memory Space Required… One Base Address Register
PCI commands Suppo
rted……. Configuration Read/Write
Memory Read/Write, 32,16, and
8-bit data transfer types
supported.
Signaling ……………………….. 5V Compliant, 3.3V Tolerant
INTA#……………………………
.
Interrupt A is used to request an
interrupt. Interrupt will occur
when the amount of new
converted data in the memory
buffer exceeds that set by the
Memory Threshold register.
Access Times………………… 8 PCI Clock Cycles for all non-
burst register accesses. Burst
read of the 512 sample memory
buffer requires three PCI clock
cycles for each sample read.
