SERIES PMC341 PCI MEZZANINE CARD SIMULTANEOUS ANALOG INPUT MODULE
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The software reset will clear this control register, the channel
enable register, counters, and the Memory Threshold register.
Channel Enable Control Register (Read/Write, 08H)
The Channel Enable Control register (bits-15 to 0) is used to
select the channels desired for conversion. Only those channels
enabled are stored into the data Memory buffer. When the
channel’s corresponding bit is set high, per the table below, the
channel’s converted data is tagged and stored into the Memory
buffer. For example, to enable channels 15, 11, and 7 through 0
the Channel Enable register must be set as 88FF hex.
Reading or writing to this register is possible via 32-bit, 16-bit
or 8-
bit data transfers. This register’s contents are cleared upon
reset.
Channel Enable Control Register
MSB
LSB
15
14
13
12
11
10
09
08
Ch15
Ch14
Ch13
Ch12
Ch11
Ch10
Ch09
Ch08
MSB
LSB
07
06
05
04
03
02
01
00
Ch7
Ch6
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
Low Bank Timer Register (Read/Write, 0CH)
Timed periodic triggering can be used to achieve precise time
intervals between conversions. The Low Bank Timer register is a
24 bit register value that controls the interval time between
conversions of all enabled channels.
The Low Bank Timer is used to control the frequency at
which the conversion cycle is repeated for all enabled channels.
For example, upon software or external trigger, channels 0 to 7
are simultaneously converted. The time programmed into the
High Bank Timer Register then determines when channels 8 to
15 are simultaneously converted. The cycle repeats when the
time programmed into Low Bank Timer has lapsed. At this time,
channels 0 to 7 will again be simultaneously converted. Thus,
the Low Bank Timer value must always be greater than the High
Bank Timer value by at least 8
seconds. If Continuous
Conversions are selected via the Control register, then
conversions will continue until disabled. See figure 1 for an
illustration of the sequence of conversions described in this
paragraph.
t1= 8us min
t1= 8us min
CH0-7
CH8-15
CH0-7
Min time= 8us
min
time
The conversion cycle repeats
High Bank
Timer Value
Time of initial
software or
external trigger
Low Bank
Timer Value
Min time = 8us + t1
0us
t0
t1
t2
Where: High Bank Timer Value must be
8
seconds
Low Bank Timer Value must be
t1 + 8
seconds
Figure1: Time line of channel bank conversions
The 24-bit Low Bank Timer value divides an 8 MHz clock
signal. The output of this Low Bank Timer is used to precisely
generate periodic trigger pulses to control the frequency at which
all enabled channels are converted. The time period between
trigger pulses is described by the following equation:
seconds
in
T
=
000
,
000
,
8
1
+
Value
T imer
Bank
Low
Hz
The following equation can be used to calculate the Low
Bank Timer value. Note, this gives the value in decimal. It must
still be converted to hex before it is written to the Low Bank Timer
register.
1
-
z)
8,000,000H
seconds
(T
=
Value
Timer
Bank
Low
Where:
T
= the desired time period between trigger pulses in seconds.
Low Bank Timer Value
can be a minimum of 63 decimal if only
channels 0 to 7 are enabled for conversion. If any channels in
the upper bank (channels 8 to 15) are also enabled, then the
minimum value is 127 decimal. The maximum value is
16,777,214 decimal.
The maximum period of time which can be programmed to
occur between simultaneous conversions is (16,777,214 + 1)
8,000,000 = 2.097151875 seconds. The minimum time interval
which can be programmed to occur is (63 + 1)
8,000,000 = 8.0
seconds. This minimum of 8.0
seconds is defined by the
minimum conversion time of the hardware given only channels 0
to 7 are enabled for conversions. If any of channels 8 to 15 are
enabled for conversion, then the minimum time that the Low
Bank Timer can be programmed is 127 decimal. The minimum
time of 16
seconds allows 8
seconds for channels 0 to 7 and
8
seconds for channels 8 to 15.
The 8
seconds maximum sample rate corresponds to a
maximum sample frequency of 125KHz. The maximum analog
input frequency should be band limited to one half the sample
frequency. An anti-aliasing filter should be added to remove
unwanted signals above 1/2 the sample frequency in the input
signal for critical applications.
Reading or writing the Low Bank Timer register is possible
with 32-bit, 16-bit or 8-
bit data transfers. This register’s contents
are cleared upon reset.
High Bank Timer Register (Read/Write, 10H)
The High Bank Timer register is a 24 bit register that controls
when the upper bank of channels 8 to 15 are converted.
The High Bank Timer is used to control the delay after
channels 0 to 7 are converted until channels 8 to 15 are
simultaneously converted. For example, upon software or
external trigger channels 0 to 7 are simultaneously converted.
Then, the time programmed into this counter determines when
channels 8 to 15 will be simultaneously converted. See figure 1
for an illustration of this sequence of events.
If a channel within the 8 to 15 bank is enabled in the Channel
Enable Control register, then the High Bank Timer register must
