SERIES PMC341 PCI MEZZANINE CARD SIMULTANEOUS ANALOG INPUT MODULE
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Interrupt Programming Example
1.
Enable PMC341 board interrupt by writing a “1” to bit 0 of
the Interrupt register at Base A 00H.
2.
Set the Memory Threshold register as desired at Base
A 14H.
3.
Interrupts can now be generated after more samples than
that set in the Memory Threshold register are available in
the Memory buffer.
General Sequence of Events for Processing an Interrupt
1.
The PMC341 asserts the Interrupt Request Line (INTA#) in
response to an interrupt condition.
2.
Determine the IRQ line assigned to the PMC341 during
system configuration (read configuration register number
15).
3.
Set up the system interrupt vector for the appropriate
interrupt.
4.
Unmask the IRQ in the system interrupt controller.
5.
The interrupt service routine pointed to by the vector set up
in step 3 starts.
6.
Interrupt service routine determines if the PMC341 has a
pending interrupt request by reading the Interrupt pending
bit-1 of the Interrupt register.
7.
Example of Generic Interrupt Handler Actions:
a)
Disable the interrupting PMC341 by writing “0” to bit-0
of the Interrupt Register to disable interrupts on the
PMC341.
b)
Service the interrupt by reading converted data resident
in the Memory buffer of the PMC341.
c)
Clear the interrupt request by writing a “1” to bit-15 of
the Interrupt register.
d)
Enable the PMC341 fo
r interrupts by writing “1” to bit-0
of the Interrupt register.
8.
Write “End-Of-Interrupt” command to systems interrupt
controller.
9.
If the PMC341’s interrupt stimulus has been removed, the
interrupt cycle is completed and the board holds the INTA#
inactive.
4.0 THEORY OF OPERATION
This section contains information regarding the hardware of
the PMC341. A description of the basic functionality of the
circuitry used on the board is also provided. Refer to the Block
Diagram shown in Drawing 4501-878 as you review this material.
FIELD ANALOG INPUTS
The field I/O interface to the carrier board is provided through
front panel connector (refer to Table 2.1).
Field I/O signals are
NON-ISOLATED.
This means that the field return and logic
common have a direct electrical connection to each other. As
such, care must be taken to avoid ground loops (see Section 2
for connection recommendations). Ignoring ground loops may
cause operational errors, and with extreme abuse, possible circuit
damage. Refer to Drawing 4501-879 for example wiring and
grounding connections.
Analog inputs and calibration voltages are selected via
analog multiplexers. PMC module control logic drives the select
signals of the multiplexer as required per the programming of the
control register.
Up to 16 differential inputs can be monitored. The multiplexer
stage directs one of two groups of eight channels for
simultaneous conversion. Channels 0 to 7 are simultaneously
selected and converted by eight individual ADC’s, and channels 8
to 15 are also simultaneously converted.
The output of the multiplexer stage feeds an instrumentation
amplifier (INAMP) stage. The INAMP has a fixed gain of one.
The INAMPs high input impedance allows measurement of
analog input signals without loading the source. The INAMP
takes in the channel’s + and - inputs and outputs a single ended
voltage proportional to it.
The output of the INAMP feeds an Analog to Digital
Converter (ADC). The ADC is a state of the art 14-bit successive
approximation converter with a built-in sample and hold circuit.
The sample and hold circuit goes into the hold mode when a
conversion is initiated. This maintains the selected channel’s
voltage constant until the ADC has accurately digitized the input.
Then, it returns to sample mode to acquire the next analog input
signal. Once a conversion has been completed, control logic on
the module automatically and simultaneously serially reads the
digitized values corresponding to the eight channels. While the
digitized values are read the inputs are in the acquire mode.
Digital noise generated by reading the newly digitized values will
not be present when the ADC transitions into the hold mode since
the analog signals are allowed to settle for an interval after the
digitized values are read. This pipelined mode of operation
facilitates a maximum system throughput with minimum system
noise.
The board contains two precision voltage references and a
ground (autozero) reference for use in calibration. A 2.5 volt
reference is used by the ADC. A 5 volt reference is used to
provide accurate auto span voltage for offset and gain correction
of the ADC and INAMP.
LOGIC/POWER INTERFACE
The logic interface to the carrier board is made through two
64-pin connectors (refer to Table 2.2 and 2.3). These connectors
also p5V and
12V power to the module. Note that the
signals in bold italic are not used.
A Field Programmable Gate-Array (FPGA) installed on the
PMC Module provides an interface to the carrier board per PMC
Module draft specification P1386.1 and PCI Local Bus
Specification 2.2. The interface to the carrier/CPU board allows
complete control of all PMC341 functions.
PCI INTERFACE LOGIC
The PCI bus interface logic is imbedded within the FPGA.
This logic includes support for PCI commands, including:
configuration read/write, and memory read/write. In addition, the
PCI target interface performs parity error detection, uses a single
4K base address register, and implements target abort, retry, and
disconnect. The PMC341 logic also implements interrupt
requests via interrupt line INTA#.
