SERIES PMC341 PCI MEZZANINE CARD SIMULTANEOUS ANALOG INPUT MODULE
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- 5 -
+CH07
22
-CH15
47
-CH07
23
COMMON
48
COMMON
24
EXT TRIGGER*
49
+CH08
25
SHIELD
50
*
Indicates that the signal is active low.
Rear J4 Field I/O Connector
The rear J4 connector provides the field I/O interface
connections. The rear connector is a 64-pin female receptacle
header (AMP 120527-1 or equivalent). Rear field I/O connector
pin assignments are shown in Table 2.2.
Table 2.2: PMC341R Rear Field I/O Pin Connections (J4)
Pin Description
Number
Pin Description
Number
+CH00
1
COMMON
33
-CH00
2
+CH11
34
COMMON
3
-CH11
35
+CH01
4
COMMON
36
-CH01
5
+CH12
37
COMMON
6
-CH12
38
+CH02
7
COMMON
39
-CH02
8
+CH13
40
COMMON
9
-CH13
41
+CH03
10
COMMON
42
-CH03
11
+CH14
43
COMMON
12
-CH14
44
+CH04
13
COMMON
45
-CH04
14
+CH15
46
COMMON
15
-CH15
47
+CH05
16
COMMON
48
-CH05
17
EXT TRIGGER*
49
COMMON
18
COMMON
50
+CH06
19
COMMON
51
-CH06
20
COMMON
52
COMMON
21
COMMON
53
+CH07
22
COMMON
54
-CH07
23
COMMON
55
COMMON
24
COMMON
56
+CH08
25
COMMON
57
-CH08
26
COMMON
58
COMMON
27
COMMON
59
+CH09
28
COMMON
60
-CH09
29
COMMON
61
COMMON
30
COMMON
62
+CH10
31
COMMON
63
-CH10
32
SHIELD
64
*
Indicates that the signal is active low.
Analog Inputs: Noise and Grounding Considerations
Differential inputs require two leads (+ and -) per channel,
and provide rejection of common mode voltages. This allows the
desired signal to be accurately measured. However, the signal
being measured cannot be floating--it must be referenced to
analog common on the PMC module and be within the normal
input voltage range.
Differential inputs are the best choice when the input
channels are sourced from different locations having slightly
different ground references and when minimizing noise and
maximizing accuracy are key concerns. See Drawing 4501-879
for analog input connections for differential-ended inputs.
Shielded cable of the shortest length possible is also strongly
recommended.
The PMC341 is non-isolated, since there is electrical
continuity between the logic and field I/O grounds. As such, the
field I/O connections are not isolated from the carrier/CPU board
and backplane. Care should be taken in designing installations
without isolation to avoid noise pickup and ground loops caused
by multiple ground connections. This is particularly important for
analog inputs when a high level of accuracy/resolution is needed.
External Trigger Input/Output
The external trigger signal on pin 49 of the front panel
connector can be programmed as an input, output, or disabled.
As an input, the external trigger must be a 5 Volt logic, TTL-
compatible, debounced signal referenced to analog common.
The external trigger signal is an active low edge sensitive signal.
That is, the external trigger signal will trigger the PMC341
hardware on the falling edge. Once the external trigger signal
has been driven low, it should remain low for a minimum of 500
nano seconds.
As an output an active-low TTL signal can be driven to
additional PMC341s, thus providing a means to synchronize the
conversions of multiple PMC341s. The additional PMC341s must
program their external trigger for signal input and convert on
external trigger only mode. See section 3.0 for programming
details to make use of this signal.
The external trigger signal can also be disabled. This
prevents external noise from falsely triggering the module. See
section 3.0 for programming details to make use of this signal.
PMC Local Bus Connector
The PMC341 module provides a 32-bit PCI interface to the
carrier via two 64 pin connectors. These connectors are 64-pin
female receptacle header (AMP 120527-1 or equivalent) which
mates to the male connector of the carrier board (AMP 120521-1
or equivalent). This provides excellent connection integrity and
utilizes gold-plating in the mating area. Threaded metric screws
and spacers are supplied with the PMC module to provide
additional stability for harsh environments (see Drawing 4501-844
for assembly details). The pin assignments of PCI local bus
connector are standard for all PMC modules according to the PCI
Mezzanine Card Specification (see Table 2.3 and 2.4).