SERIES PMC341 PCI MEZZANINE CARD SIMULTANEOUS ANALOG INPUT MODULE
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PCI Configuration Address Space
When the computer is first powered-
up, the computer’s
system configuration software scans the PCI bus to determine
what PCI devices are present. The software also determines the
configuration requirements of the PCI card.
The system software accesses the configuration registers to
determine how many blocks of memory space the carrier
requires. It then p
rograms the PMC module’s configuration
registers with the unique memory base address.
The configuration registers are also used to indicate that the
PMC module requires an interrupt request line. The system
software then programs the configuration registers with the
interrupt request line assigned to the PMC module.
Since this PMC module is relocatable and not fixed in
address space, this module’s device driver must use the mapping
information stored in the module’s Configuration Space registers
to determine where the module is mapped in memory space and
which interrupt line will be used.
Configuration Registers
The PCI specification requires software driven initialization
and configuration via the Configuration Address space. This
PMC module provides 256 bytes of configuration registers for this
purpose. The PMC341 contains the configuration registers,
shown in Table 3.1, to facilitate Plug-and-Play compatibility.
The Configuration Registers are accessed via the
Configuration Address and Data Ports. The most important
Configuration Registers are the Base Address Registers and the
Interrupt Line Register which must be read to determine the base
address assigned to the PMC341 and the interrupt request line
that goes active on a PMC341 interrupt request.
Table 3.1 Configuration Registers
Reg.
Num.
D31 D24
D23 D16
D15
D8
D7
D0
0
Device ID=4D4D
Vendor ID= 16D5
1
Status
Command
2
Class Code=118000
Rev ID=00
3
BIST
Header
Latency
Cache
4
32-bit Memory Base Address for PMC341
4K-Byte Block
5 : 10
Not Used
11
Subsystem ID=0000
Subsystem Vendor
ID=0000
12
Not Used
13,14
Reserved
15
Max_Lat
Min_Gnt
Inter. Pin
Inter. Line
MEMORY MAP
This board is allocated a 4K byte block of memory that is
addressable in the PCI bus memory space to control the
acquisition of analog inputs from the field. As such, three types
of information are stored in the memory space: control, status,
and data.
The memory space address map for the PMC341 is shown in
Table 3.2. Note that the base address for the PMC341 in
memory space must be added to the addresses shown to
properly access the PMC341 registers. Register accesses as 32,
16, and 8-bit in memory space are permitted.
Table 3.2: PMC341 Memory Map
2
Base
Addr+
D31
D16
D15
D00
Base
Addr+
03
Not Used
1
Interrupt Register
00
07
Control Register
04
0B
Not Used
1
Channel Enable
Control
08
0F
Low Bank Timer
0C
13
High Bank Timer
10
17
Not Used
1
Memory Threshold
Register
14
1B
Not Used
Bits-31 to 01
Start Convert
Bit-0
18
1F
Not Used
1
Reference Voltage
Access Register
1C
23
Not Used
1
Reference Voltage
Data & Status
20
27
Not Used
1
Reference Voltage
Write Enable Code
3
24
29
Not Used
1
28
7FF
Not Used
1
7FC
803
1
st
Memory Location
Not Used(31:20), Tag bits(19:16),
Data(15:0)
800
FFF
512
th
Memory Location
Not Used(31:20), Tag bits(19:16),
Data(15:0)
FFC
Notes (Table 3.2):
1. The PMC341 will return 0 for all addresses that are "Not
Used".
2. All Reads and writes are 8 clock cycles.
3. This byte is reserved for use at the factory to enable writing of
the reference voltage. Write only byte value = “A3”.
This memory map reflects byte accesses using the “Little
Endian” byte ordering format. Little Endian uses even-byte
addresses to store the low-order byte. The Intel x86 family of
microprocessors uses “Little Endian” byte ordering. Big Endian is
the convention used in the Motorola 68000 microprocessor family
and is the VMEbus convention. In Big Endian, the lower-order
byte is stored at odd-byte addresses.
Interrupt Register, (Read/Write) - (Base + 00H)
This read/write register is used to enable board interrupt,
determine the pending status of interrupts, and release an
interrupt.
The function of each of the interrupt register bits are
described in Table 3.3. This register can be read or written with
either 8-bit, 16-bit, or 32-bit data transfers. A power-up or system
reset sets all interrupt register bits to 0.
