SERIES PMC341 PCI MEZZANINE CARD SIMULTANEOUS ANALOG INPUT MODULE
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All register accesses to the PMC341 require 8 PCI clock
cycles with the exception of burst read operations which will be
implemented in three PCI clock cycles.
BURST READ OF PMC341 MEMORY
Burst read of PMC341 memory buffer will allow a 40Mbyte
per second data read rate. With every three PCI clock cycles a
new data sample is read from the memory buffer. The PMC341
will automatically stop the burst operation upon reaching the end
of the Memory buffer.
Note that, burst mode read operations can only be used on
hardware that is prefetchable. The PMC341 is prefetchable since
it makes use of RAM, not FIFO, memory to retrieve sample data.
Prefetchable hardware requires read operations that do not
destroy the data. In burst read operations, it is possible for the
system to read more data from a PCIbus module than is actually
delivered to its destination. When this happens, given a FIFO
implementation, the data would be forever destroyed/lost.
However with the PMC341 RAM implementation, the undelivered
data could be read again. Reading of Memory buffer can start at
any address location allowing access to any of the 512 available
samples.
CONVERSION CONTROL LOGIC
All logic to control data conversions is imbedded in the PMC
module’s FPGA. The control logic of the module is responsible
for controlling the programmed mode of operation. Once the
PMC module has been configured, the control logic performs the
following:
Controls Multiplexers for selection of channel data.
Controls serial transfer of data from the eight ADC’s to
the FPGA memory buffer.
Controls conversion rate as user programmed.
Provides memory buffer switch control.
Provides external or internal trigger control.
Controls read and write access to the reference voltage
value stored in memory.
Controls interrupt requests to the carrier/CPU and
responds to interrupt select cycles.
MULTIPLEXER CONTROL CIRCUITRY
Analog channels are multiplexed into the ADC’s. The
multiplexers allows the programmable selection of analog
channel data or the auto span and auto zero calibration voltages.
When selected for differential analog input of channel data,
channels 0 to 7 are automatically selected for simultaneous
conversion first. Channels 0 to 7 are converted upon an external
trigger or software start convert. Then, 1.25
seconds after
channels 0 to 7 are converted the multiplexers swith to channels
8 to 15 for input to the ADC’s. This provides a setup time, for
channels 8 to 15, of the High Bank time minus 1.25
seconds.
DATA TRANSFER FROM ADC TO FPGA
A 16-
bit serial shift register is implemented in the module’s
FPGA for each of the eight channels. Internal FPGA counters
are used to synchronize the transfer of digitized data from the
A/D converters to the memory buffer. Only the channels enabled
for conversion are stored in memory and tagged for channel
identification.
CONVERSION COUNTER
The ADC conversion rate is controlled by a conversion
counter, which is a 24-bit counter implemented in the FPGA. The
counter provides variable time periods up to 2.0889 seconds.
The output of this counter is compared to the value stored in the
Low Bank Timer register to trigger the start of new conversions
for the continuous mode of operation. The output of the
conversion counter is also compared to the value stored in the
High Bank Timer register to determine when the second bank of
channels (8 through 15) are to be simultaneously triggered for
conversion.
MEMORY BUFFER SWITCH CONTROL
Two 512 sample memory buffers are provided in the FPGA
logic to control simultaneous data acquisition and data reading
via the PCI bus. One memory buffer accepts new data input
samples along with a channel tag value. The other memory
buffer is available for data reading at PCI burst data rates over
the PCI bus. The Memory Threshold value is used to control
transition between the two 512 sample memory buffers. When
the analog input memory buffer contains more samples then the
Memory Threshold value the memory banks will switch. See
section 3.0 for programming details and use of the Memory
Threshold register.
EXTERNAL TRIGGER
The external trigger connections are made via pin 49 of the
Field I/O Connector. For all modes of operation, when the
external trigger is enabled as an input via bits 4 and 5 of the
control register, the falling edge of the external trigger will initiate
simultaneous conversions for channels 0 to 7. Once the external
trigger signal has been driven low, it should remain low for a
minimum of 250n seconds for proper external trigger operation.
The external trigger input signals must be TTL compatible. The
PMC341 uses a diode clamping circuit to protect the board from
external trigger signals that violate the 5 volt logic (TTL)
requirement.
As an output, an active-low TTL signal is driven from the
PMC module. The trigger pulse generated is low for 500n
seconds, typical. See section 3.0 for programming details to
make use of this signal.
INTERRUPT CONTROL LOGIC
The PMC341 can be configured to generate an interrupt
using a programmable Memory Threshold level. When the
memory buffer has more samples than set in the Memory
Threshold register the PMC interrupt signal INTA# is driven active
to the carrier/CPU to request an interrupt. Bit-1 of the Interrupt
register (at Base A 0H) can be read to identify a pending
interrupt. The interrupt release mechanism employed is release
on register access. The PMC341 will release the interrupt
request when bit-15 of the Interrupt register (at Base A
0H) is set to a logic “1”.
REFERENCE VOLTAGE MEMORY CONTROL LOGIC
The FPGA of the PMC341 module contains control logic that
implements read and write access to reference voltage memory.
The reference voltage memory (EEPROM) contains an ASCII null
