Major Chips Description
2-15
Table 2-2
PCI1250 Terminal Functions
Name
No.
I/O Type
Function
CINT
Y04
A10
I
CardBus interrupt. This signal is asserted low by a
CardBus PC Card to request interrupt servicing
from the host.
CIRDY
T02
A16
I/O
CardBus initiator ready. CIRDY indicates the
CardBus initiator's ability to complete the current
data phase of the transaction. A data phase is
completed upon a rising edge of CCLK where both
CIRDY and CTRDY are asserted. Until CIRDY and
CTRDY are both sampled asserted, wait states are
inserted.
CPERR
P02
B17
I/O
CardBus Parity Error. This signal is used to report
parity errors during CardBus transactions, except
during special cycles. It is driven low by a target
two clocks following that data when a parity error is
detected.
CREQ
Y01
D12
I
CardBus Request. This signal indicates to the
arbiter that the CardBus PC Card desires use of the
CardBus bus as an initiator
CSERR
V05
B10
I
CardBus System Error. This signal reports address
parity errors and other system errors which could
lead to catastrophic results. CSERR is driven by the
card synchronous to CCLK but ceasserted by a
weak pull-up, and may take a few CCLK periods.
The PCI1250A can report CSERR to the system by
assertion of SERR on the PCI interface.
CSTOP
R01
C17
I/O
CardBus Stop Signal. This signal is driven by a
CardBus target to request the initiator to stop the
current CardBus transaction. This signal is used for
target disconnects, and is commonly asserted by
target devices which do not support burst data
transfers.
CSTSCHG
V06
A09
I
CardBus Status Change. CSTSCHG is used to alert
the system to a change in the card's status, and is
used as a wake-up mechanism.
CTRDY
P04
C16
I/O
CardBus Target Ready. CTRDY indicates the
CardBus target's ability to complete the current
data phase of the transaction. A data phase is
completed upon a rising edge of CCLK where both
CIRDY and CTRDY are asserted; until which wait
states are inserted
CVS1
CVS2
Y03
U03
A11
B14
I/O
CardBus Voltage Sense 1 and Voltage Sense 2.
These signals are used in conjunction with card
detect signals to identify card insertion and
interrogate cards to determine the operating voltage
and card type.
Содержание 390 Series
Страница 14: ...1 2 Service Guide 1 2 System Board Layout 1 2 1 Mainboard Figure 1 1 PCB No 96183 1A Mainboard Layout Top ...
Страница 15: ...System Introduction 1 3 Figure 1 2 PCB No 96183 1A Mainboard Layout Bottom ...
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Страница 97: ...Major Chips Description 2 51 Figure 2 5 FDC37C67 QFP Pin Diagram ...
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