Acer 390 Series, Руководство по обслуживанию

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Major Chips Description 2-67
Table 2-8 65555 Pin Functions
Ball Pin Name Type Active Description
L4 DEVSEL# S/TS Low Device Select. Indicates the current target has
decoded its address as the target of the current
access
L2 PERR# S/TS Low Parity Error. This signal reports data parity errors
(except for Special Cycles where SERR# is
used). The PERR# pin is Sustained Tri-state. The
receiving agent will drive PERR# active two
clocks after detecting a data parity error PERR#
will be driven high for one clock before being tri-
stated as with all sustained tri state signals.
PERR# will not report status until the chip has
claimed the access by asserting DEVSEL# and
completing the data phase.
L3 SERR# OD Low System Error. Used to report system errors
where the result will be catastrophic (address
panty error, data panty errors for Special Cycle
commands, etc.). This output is actively driven
for a single PCI clock cycle synchronous to BCLK
and meets (he same setup and hold time
requirements as all other bused signals. SERR#
is not driven high by the chip after being
asserted, but is pulled high only by a weak pull-
up provided by the system. Thus, SERR# on the
PCI bus may take two or three clock periods to
fully return to an inactive state.
Note: S/TS stands for "Sustained Tri-state". These signals are driven by only one device at a time, are
driven high for one clock before released, and are not driven for at least one cycle after being
released by the previous device. A pull-up provided by the bus controller is used to maintain an
inactive level between transactions.
All signals listed above are powered by BVCC and GND. ROMOE# is powered by
MVCC and GND.