2-70
Service Guide
Table 2-8
65555 Pin Functions
Ball
Pin Name
Type
Active
Description
J18
J17
H19
G20
H18
G19
F20
G18
F19
D20
E19
F17
E18
D19
MC0
MC1
MC2
MC3
MC4
MC5
MC6
MC7
MC8
MC11
MC12
MC13
MC14
MC15
I/0
l/O
l/O
l/O
l/O
l/O
l/O
l/O
l/O
I/0
l/O
l/O
l/O
l/O
High
High
High
High
High
High
High
High
High
High
High
High
High
High
DRAM data bits 32-47.
R20
P19
N18
P20
N19
M17
M18
N20
M19
M20
L18
L19
L20
L17
K17
K20
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11(RMA16)
MD12(rma17)
MD13
MD14
MD15
I/0
l/O
l/O
l/O
l/O
l/O
l/O
l/O
l/O
I/0
l/O
l/O
l/O
l/O
l/O
l/O
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
DRAM data bits 48-63.
MD11-12 are also ROM addresses 16-17.
MD11 and MD12, along with MB0 through MB15,
also serve as the address bus for the BIOS ROM
during startup (i.e., beore the system enables the
graphics controller memory interface).
C11
K18#
RAS0#
PAS1#
Out
Out
Low
Low
RAS for DRAM Bank 0 (128K, 256K, or 512K by
64-bit).
RAS for DRAM Bank 1.
C6
ROMOE#(MCLKOUT)
Out
Low
Output Enable for BIOS ROM. May be
configured as MCLK output in test mode.
D11
A11
C16
B17
H20
J19
P18
R19
ASAL#
ASAH#
CASBL#
CASBH#
ASCL#
ASCH#
ASDL#
CASH#
Out
Out
Out
Out
Out
Out
Out
Out
High
High
High
High
High
High
High
High
CAS for dual-CAS EDO DRAM.
Memory data byte mask signals. one mask
signal for each of the eight data bytes in the 64-
bit Qword. The masking is performed on a per-
byte basis. A given byte is masked when the
signal is high, or enabled when the signal is low.
Masking is needed on write operations to specify
which bytes in the 64-bit word are being written.
B11
WEA#
Out
Low
MA[15:0] write enable for dual-CAS EDO DRAM
A18
WEB#
Out
Low
MB[15:0] write enable for dual-CAS EDO DRAM
J20
WEC#
Out
Low
MC[15:0] write enable for dual-CAS EDO DRAM
T20
WED#
Out
Low
MD[15:0] write enable for dual-CAS EDO DRAM
Note:
All signals listed above are powered by MVCC and GND.
The 8 bytes comprising each 64-bit Qword are labeled AL, AH, BL, BH, CL, CH, DL, and DH.
There is a separate byte mask signal for each byte. Up to two banks can be supported, with
RAS0# controlling the first bank and RAS l# controlling the second bank. The address, data and
byte mask signals are the same for each bank.
Содержание 390 Series
Страница 14: ...1 2 Service Guide 1 2 System Board Layout 1 2 1 Mainboard Figure 1 1 PCB No 96183 1A Mainboard Layout Top ...
Страница 15: ...System Introduction 1 3 Figure 1 2 PCB No 96183 1A Mainboard Layout Bottom ...
Страница 96: ...2 50 Service Guide 2 3 3 Pin Configuration Figure 2 4 FDC37C67 TQFP Pin Diagram ...
Страница 97: ...Major Chips Description 2 51 Figure 2 5 FDC37C67 QFP Pin Diagram ...
Страница 102: ...2 56 Service Guide 2 3 6 Block Diagram Figure 2 6 FDC37C67 Block Diagram ...
Страница 111: ...Major Chips Description 2 65 2 4 4 3 Bottom View BGA Ball Assignments Figure 2 8 65555 BGA Ball Assignments Bottom View ...
Страница 126: ...2 80 Service Guide 2 5 4 1 Functional Block Diagram Figure 2 10 M38813 Block Diagram ...
Страница 128: ...2 82 Service Guide 2 6 2 Pin Diagram Figure 2 11 YMF715 Block Diagram ...
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