2-34
Service Guide
Table 2-4
M1531 Numerical Pin List
No.
Name
Type
No.
Name
Type
No.
Name
Type
J17
MD43
I/O
T18
RASJ1
O
R15
VCC_C
P
J19
MD44
I/O
U20
RASJ2
O
R7
VCC_A
P
H16
MD45
I/O
U19
RASJ3
O
R6
VDD5
P
H18
MD46
I/O
U18
RASJ4
O
N15
VDD5S
P
H20
MD47
I/O
V20
RASJ5
O
H4
WRJ
I
G17
MD48
I/O
R16
RASJ6
O
--
--
--
G19
MD49
I/O
R17
RASJ7
O
--
--
--
F16
MD50
I/O
D13
REQJ0
I
--
--
--
F18
MD51
I/O
C13
REQJ1
I
--
--
--
F20
MD52
I/O
B13
REQJ2
I
--
--
--
E17
MD53
I/O
A13
REQJ3
I
--
--
--
E19
MD54
I/O
N16
REQJ4
I/O
--
--
--
D16
MD55
I/O
E5
RSTJ
I
--
--
--
D18
MD56
I/O
E8
SERRJ
I/O
--
--
--
D20
MD57
I/O
F3
SMIACTJ
I
--
--
--
C18
MD58
I/O
C8
STOPJ
I/O
--
--
--
C20
MD59
I/O
P17
SUSPENDJ
I
--
--
--
B19
MD60
I/O
U12
TIO0
I/O
--
--
--
A18
MD61
I/O
U13
TIO1
I/O
--
--
--
A20
MD62
I/O
V14
TIO2
I/O
--
--
--
B17
MD63
I/O
Y14
TIO3
I/O
--
--
--
H5
MIOJ
I
W14
TIO4
I/O
--
--
--
A17
MPD0
I/O
Y15
TIO5
I/O
--
--
--
2.2.2 M1533
The M1533 is a bridge between PCI and ISA bus, providing full PCI and ISA compatible functions.
This chip has Integrated System Peripherals (ISP) (2 x 82C59 and serial interrupt, 1 x 82C54),
advanced features (Type F and Distributed DMA) in the DMA controller (2 x 82C54), PS/2
keyboard/mouse controller, two-channel dedicated IDE master controller with Ultra-33
specification, System Management Bus (SMB), and two OpenHCI 1.0a USB ports. The ACPI
(Advanced Configuration and Power Interface) and PCI 2.1 (Delayed Transaction & Passive
Release) specification have also been implemented. Furthermore, this chip supports the
Advanced Programmable Interrupt Controller (APIC) interface for Multiple-Processors system.
The M1533 also supports the deep flexible green function for the best green system. It can
connect to the ALi Pentium North Bridge (M1521/M1531/M1541) and ALi Pentium Pro North Bridge
(M1615) to provide the best system solution. One eight-byte bidirectional line buffer is provided for
ISA/DMA master memory read/writes; one 32-bit wide posted write buffer is provided for PCI
memory write & I/O write (for audio) cycles to the ISA bus, to provide a PCI to ISA IRQ routing
table, and
level-to-edge trigger transfer.
Содержание 390 Series
Страница 14: ...1 2 Service Guide 1 2 System Board Layout 1 2 1 Mainboard Figure 1 1 PCB No 96183 1A Mainboard Layout Top ...
Страница 15: ...System Introduction 1 3 Figure 1 2 PCB No 96183 1A Mainboard Layout Bottom ...
Страница 96: ...2 50 Service Guide 2 3 3 Pin Configuration Figure 2 4 FDC37C67 TQFP Pin Diagram ...
Страница 97: ...Major Chips Description 2 51 Figure 2 5 FDC37C67 QFP Pin Diagram ...
Страница 102: ...2 56 Service Guide 2 3 6 Block Diagram Figure 2 6 FDC37C67 Block Diagram ...
Страница 111: ...Major Chips Description 2 65 2 4 4 3 Bottom View BGA Ball Assignments Figure 2 8 65555 BGA Ball Assignments Bottom View ...
Страница 126: ...2 80 Service Guide 2 5 4 1 Functional Block Diagram Figure 2 10 M38813 Block Diagram ...
Страница 128: ...2 82 Service Guide 2 6 2 Pin Diagram Figure 2 11 YMF715 Block Diagram ...
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