Acer 390 Series, Руководство по обслуживанию

Страница: 72 / 204

2-26 Service Guide
Table 2-3 M1531 Signal Descriptions
Signal Type Description
CLKEN[1]/
GNTJ[4] O
Group C
SDRAM Clock Enable Copy 1 or PCI Master Grant. This signal is used as
SDRAM clock enable copy 1 to do self refresh during suspend. It can also be
used as grant signal of the fifth PCI master. This function is controlled by
Index -5Dh bit 1.
Secondary Cache Interface 3.3V/2.5V Tolerance
CADVJ O
Group A
Synchronous SRAM Advance. This signal will make PBSRAM/Memory Cache
internal burst address counter advance.
CADSJ O
Group A
Synchronous SRAM Address Strobe. This signal connects to PBSRAM/
Memory Cache ADSCJ.
CCSJ O
Group A
Synchronous SRAM Chip Select. This signal connects to PBSRAM/Memory
Cache CE1J to mask ADSPJ and enable ADSCJ sampling.
GWEJ O
Group A
Synchronous SRAM Global Write Enable. This signal will write all the byte
lanes data into PBSRAM/Memory Cache.
COEJ O
Group A
Synchronous SRAM Output Enable. This signal will enable the data output
driving of PBSRAM/Memory Cache.
BWEJ O
Group A
Synchronous SRAM Byte-Write Enable. This signal connects to byte write
enable of PBSRAM/Memory Cache.
TIO[10]/
MWEJ[1]/
MKREFRQJ
I/O
Group C
SRAM Tag[10] or another copy of MWEJ or DRAM Cache MKREFRQJ. This
pin is used for multifunction. It can be SRAM tag address bit 10, or another
copy of MWEJ connected to DRAM, or MKREFRQJ connected to DRAM
Cache. Refer to Register Index-41h bit 6, bit3 and bit0 description.
TIO[9]/
SRASJ[1] I/O
Group C
SRAM Tag[9] or Synchronous DRAM (SDRAM) RAS copy 1. This pin is used
for multifunction. It can be SRAM tag address bit 9, or another copy of
SRASJ connected to SDRAM. Refer to Register Index-41h bit3 and bit0
description.
TIO[8]/
SCASJ[1] I/O
Group C
SRAM Tag[8] or Synchronous DRAM (SDRAM) CAS copy 1. This pin is used
for multifunction. It can be SRAM tag address bit 8, or another copy of
SCASJ connected to SDRAM. Refer to Register Index-41h bit3 and bit0
description.
TIO[7:0] I/O
Group B
SRAM Tag[7:0]. This pin contains the L2 tag address for 256-KB L2 caches.
TIO[6:0] contain the L2 tag address and TIO7 contains the L2 cache valid bit
for 512-KB caches. TIO[5:0] contain L2 tag address, TIO7 contains L2 cache
valid bit and TIO6 contains the L2 cache dirty bit for 1-MB cache. Refer to
index-41h cache configuration table.
TAGWEJ O
Group B
Tag Write Enable. This signal, when asserted, will write into the external tag
new state and tag addresses.
PCI Interface 3.3V/2.5V Tolerance
AD[31:0] I/O
Group B
PCI Address and Data Bus Lines. These lines are connected to the PCI bus.
AD[31:0] contain the information of address or data for PCI transactions.
CBEJ[3:0] I/O
Group B
PCI Bus Command and Byte Enables. Bus commands and byte enables are
multiplexed in these lines for address and data phases, respectively.
FRAMEJ I/O
Group B
Cycle Frame of PCI Buses. This indicates the beginning and duration of a
PCI access. It will be as an output driven by M1531 on behalf of CPU, or as
an input during PCI master access.