Acer 390 Series, Руководство по обслуживанию

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Major Chips Description 2-69
Table 2-8 65555 Pin Functions
Ball Pin Name Type Active Description
Display Memory Interface
D18
Cl9
B20
C18
A20
Bl9
Al9
B18
C17
D16
AA0 (CFG0)
AAI (CFG1)
AA2 (CFG2)
AA3 (CFG3)
AA4 (CFG4)
AA5 (CFG5)
AA6 (CFG6)
AA7 (CFG7)
AA8 (CFG8)
AA9 (CFG9)
I/O
l/O
l/O
l/O
l/O
I
/0
l/O
l/O
l/O
I/O
Both
Both
Both
Both
Both
Both
Both
Both
Both
Both DRAM address bus for Bank 0 and Bank
AA0 through AA9 also serve as configuration bits
CFG0 through CFG9. Please see the
descriptions for registers XR70 and XR71 for
complete details on configuration
D10
A10
B10
C10
A9
B9
A8
C9
B8
A7
C8
B7
A6
C7
B6
A5
MA0 (TM0)
MA1 (TM1)
MA2 (CFG10)
MA3 (CFG11)
MA4 (CFG12)
MA5 (CFG13)
MA6 (CFG14)
MA7 (CFG15)
MA8 (RMD0)
MA9 (RMDI)
MA10 (RMD2)
MA11 (RMD3)
MA12 (RMD4)
MA13 (RMD5)
MA14 (RMD6)
MA15 (RMD7)
I/O
l/O
l/O
I/O
l/O
l/O
l/O
I/O
l/O
l/O
I/O
l/O
l/O
I/O
l/O
l/O High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High DRAM data bits 0-15.
MA0 is also a test mode signal (Tri-Stale
Enable).
MA1 is also a test mode signal (ICT Enable).
MA2 through MA7 also serve as configuration
bits CFG10 through CFG15. Please see the
description for register XR71 for complete details
on configuration options.
MA8 through MA15 are also serve as the data
bus for the BIOS ROM during system startup
(i.e., before the system enables the graphics
controller memory interface).
D15
B16
A17
C15
A16
B15
C14
A15
B14
C13
A14
B13
D12
C12
A13
B12 MB0 (RMA0)
MBI (RMAI)
MB2 (RMA2)
MB3 (RMA3)
MB4 (RMA4)
MB5 (RMA5)
MB6 (RMA6)
MB7 (RMA7)
MB8 (RMA8)
MB9 (RMA9)
MB10 (RMA10)
MB11 (RMA11)
MB12 (RMA12)
MB13 (RMA13)
MB14 (RMA14)
MB15 (RMA15)
I/0
l/O
l/O
l/O
l/O
l/O
l/O
l/O
l/O
I/0
l/O
l/O
l/O
l/O
l/O
l/O
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High DRAM data bits 16-31.
MB0 through MB15, along with MDI I and MD12,
also serve as the address bus for the BIOS ROM
during startup (i.e., before he system enables the
graphics controller memory interface).
Normally, a separate graphics BIOS ROM is not
required in portable computer designs, because
the graphics BIOS is normally placed in the
same ROM devices as the system BIOS.
However, this graphics controller provides this
BIOS ROM interface capability for use in
development systems and add-in cards for flat
panel displays. Since the PCI bus specification
requires only one load on the PCI bus for each
PCI device, this BIOS ROM interface is provided
to allow access to the BIOS ROM through the
graphics controller chip, itself.