Acer 390 Series, Руководство по обслуживанию

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2-66 Service Guide
2.4.4.4 Pin Functions
Table 2-8 65555 Pin Functions
Ball Pin Name Type Active Description
PCI Bus Interface
C1 RST# In Low Reset. This input sets all signals and registers in
the chip to a known slate. All outputs from the
chip are tri-stated or driven to an inactive state.
This pin is ignored during Standby mode
(STNDBY# pin low). The remainder of the
system (therefore the system bus) may be
powered down if desired (all bus output pins
are tri-stated in Standby mode).
D2 BCLK In High Bus Clock. This input provides the timing
reference for all PCI bus transactions. All bus
inputs except RESET# are sampled on the rising
edge of BCLK. BCLK may be any frequency from
DC to 33MHz.
M1 PAR I/O High Parity. This signal is used to maintain even parity
across AD031 and C/BE0-3#. PAR is stable and
valid one clock after the address phase. For data
phases PAR is stable and valid one clock after
either IRDY# is asserted on a write transaction or
TRDY# is asserted on a read transaction. Once
PAR is valid, it remains valid until one clock after
the completion of the current data phase (i.e.,
PAR has the same timing as AD0-3I but delayed
by one clock). The bus master drives PAR for
address and write data phases; the target drives
PAR for read data phases.
K2 FRAME# In Low Cycle Frame. Driven by the current master to
indicate the beginning and duration of an access.
Assertion indicates a bus transaction is
beginning (while asserted, data transfers
continue); de-assertion indicates the transaction
is in the final data phase
K1 IRDY# In Low Initiator Ready. Indicates the bus master's ability
to complete the current data phase of the
transaction. During a write, IRDY# indicates valid
data is present on AD0-3 1; during a read it
indicates the master is prepared to accept data.
A data phase is completed on any clock when
both IRDY# and TRDY# are sampled then
asserted (wait cycles are inserted until this
occurs).
K4 TRDY# S/TS Low Target Ready. Indicates the target's ability to
complete the current data phase of the
transaction. During a read, TRDY# indicates that
valid data is present on AD0-3 1; during a write it
indicates the target is prepared to accept data. A
data phase is completed on any clock when both
IRDY# and TRDY# are sampled then asserted
(wait cycles are inserted until this occurs).
L1 STOP# S/TS Low Stop. Indicates the current target is requesting
the master to stop the current transaction.