MC96FR116C
114
November, 2018 Rev.1.8
0
0
0
V0 (56/64 VDD_IR)
0
0
1
V1 (57/64 VDD_IR)
0
1
0
V2 (58/64 VDD_IR)
0
1
1
V3 (59/64 VDD_IR)
1
0
0
V4 (60/64 VDD_IR)
1
0
1
V5 (61/64 VDD_IR)
1
1
0
V6 (62/64 VDD_IR)
1
1
1
V7 (63/64 VDD_IR)
IRCC1 (IR Capture Register 1)
DE
H
7
6
5
4
3
2
1
0
IRCEN
IRIIF
IREDGE1
IREDGE0
-
IRPOL
SINGLE
PHASE
R/W
R
R/W
R/W
-
R/W
R/W
R/W
Initial value : 00
H
IRCEN
Control operation mode of WT, T2 and T3
0
IR capture mode is disabled, normal timer function
1
IR capture mode is enabled (WT, T2 and T3 modules are
under control of this bit)
IRIIF
Interrupt flag of IRI input. This flag is cleared by writing ‘0’ to this bit
field or interrupt is serviced.
0
No IRI input is generated
1
IRI interrupt is generated on the condition by IREDGE[1:0]
bits
IREDGE[1:0]
Select IRI interrupt triggering condition.
00
IRI interrupt is disabled
01
Interrupt is triggered on falling edge of IRI input
10
Interrupt is triggered on rising edge of IRI input
11
Interrupt is triggered on both edge of IRI input
IRPOL
Select the polarity of WT input source.
0
The inverted signal from IRAMP output(=COMP_OUT) or
PAD_REM_OUT input becomes the input source of WT.
1
The multiplexed output of IRAMP output(=COMP_OUT) or
PAD_REM_OUT input becomes the input source of WT.
SINGLE
Select carrier capture numbers. Used with the PHASE bit.
0
Capture continuously until WTIR overflows(=WTIR reaches
to pre-defined value, WTDR1 and WTDR0)
1
Capture first 3 edges of carrier signal
PHASE
Select carrier capture sequence. Used with the SINGLE bit.
0
Capture sequence is 1
st
Falling
Rising
Falling edge
1
Capture sequence is 1
st
Rising
Falling
Rising edge
IRCC2 (IR Capture Register 2)
DF
H
7
6
5
4
3
2
1
0
T3IR
T2IR
-
-
T3EDGE1
T3EDGE0
T2EDGE1
T2EDGE0
R/W
R/W
-
-
R/W
R/W
R/W
R/W
Initial value : 00
H
T3IR
Make T3 to calculate the number of incoming carrier signal if CAP3
bit in T3CR bit is not ‘1’.
