Abov MC96FR116C Series, Руководство пользователя

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MC96FR116C
November, 2018 Rev.1.8 73
11.2.2 Block Diagram
÷ 256
P
re
sc
a
le
r
÷16
÷2048
÷32
. . .
3
BCK
BCLKS
BITR BITIF
Overflow
8-bit up-counter
BCCR
ACK
From CPU
Interal BUS line
BCLR
Read
BIT Interrupt
WDT Source Clock
0
1
[8B
H
]
[8C
H
]
SCLK
(System Clock)
RING
OSC
(1MHz)
11.2.3 Register Map
Name Address Dir Default Description
BCCR 8B
H
R/W 77
H
BIT Clock Control Register
BITR 8C
H
R 00
H
Basic Interval Timer Register
Table 11-2 Register Map of BIT
11.2.4 Register Description
BCCR (BIT Clock Control Register) 8B
H
7 6 5 4 3 2 1 0
BITF BCK2 BCK1 BCK0 BCLR PRD2 PRD1 PRD0
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value : 57
H
BITF Reflects the state of BIT interrupt. To clear this flag, write ‘0’ to this bit
position. The BIT interrupt occurs when BIT counter reaches to the pre-
defined value. The interrupt interval is decided from BCK[2:0] and
PRD[2:0] bits.
0
BIT Interrupt not occurred
1 BIT Interrupt occurred
BCK[2:0] BCK2 BCK1 BCK0 BIT Clock BIT Interrupt Period
NOTE
0 0 0 f
SYS
/2^4 1.024ms
0 0 1 f
SYS
/2^5 2.048ms
0 1 0 f
SYS
/2^6 4.096ms
0 1 1 f
SYS
/2^7 8.192ms
Figure 11-2 Block Diagram of BIT