MC96FR116C
40
November, 2018 Rev.1.8
8.2 IRAM
Internal Data Memory is mapped in Figure 8-2. The memory space is shown divided into three blocks,
which are generally referred to as the Lower 128, the Upper 128, and SFR space.
Internal Data Memory addresses are always one byte wide, which implies an address space of only
256 bytes. However, the addressing modes for internal RAM can in fact accommodate 384 bytes,
using a simple trick. Direct addresses higher than 7F
H
access one memory space, and indirect
addresses higher than 7F
H
access a different memory space. Thus Figure 8-2 shows the Upper 128
and SFR space occupying the same block of addresses, 80
H
through FF
H
, although they are
physically separate entities.
The Lower 128 bytes of RAM are present in all devices using
MCS-51
devices as mapped in Figure 8-
2. The lowest 32 bytes are grouped into 4 banks of 8 registers. Program instructions call out these
registers as R0 through R7. Two bits in the Program Status Word (PSW) select which register bank is
in use. This allows more efficient use of code space, since register instructions are shorter than
instructions that use direct addressing.
The next 16 bytes above the register banks form a block of bit-addressable memory space. The MCS-
51 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this area can
be directly addressed by these instructions. The bit addresses in this area are 00
H
through 7F
H
.
All of the bytes in the Lower 128 can be accessed by either direct or indirect addressing. The Upper
128 can only be accessed by indirect addressing. These spaces are used for user RAM and stack
pointer.
Upper
128 Bytes
Internal RAM
(Indirect Addressing)
Special Function
Registers
128 Bytes
(Direct Addressing)
Lower
128 Bytes
Internal RAM
(Direct or Indirect
Addressing)
FF
H
80
H
7F
H
00
H
FF
H
80
H
Figure 8-2 DATA MEMORY (IRAM)
