4. FDC Description (82078)
22
Boot Drive Selection Options
BOOTSEL1
BOOTSEL0
Mapping:
DS0 --> FDS0, ME0 --> FDME0
0
0
DS1 --> FDS1, ME1 --> FDME1
DS2 --> FDS2, ME2 --> FDME2
DS0 --> FDS1, ME0 --> FDME1
0
1
DS1 --> FDS0, ME1 --> FDME0
DS2 --> FDS2, ME2 --> FDME2
DS0 --> FDS2, ME0 --> FDME2
1
0
DS1 --> FDS1, ME1 --> FDME1
DS2 --> FDS0, ME2 --> FDME0
1
1
Reserved
Datarate Select Register (DSR)
3F4h Default
This register is included for compatibility with the 82072 floppy controller and is write-
only. Changing the data rate changes the timings of the drive control signals. Therefore,
to avoid violating drive timings when changing data rates, choose a drive timing such
that its fastest data rate will not violate the timing.
7
6
5
4
3
2
1
0
DRATE
SEL1
S/W
RESET
PRE-
COMP
POWER
DOWN
PDOSC
DRATE
SEL0
2
PRE-
COMP
1
PRE-
COMP
0
Datarate Select Register
Bit 7, S/W RESET, behaves the same as DOR RESET except that this reset is self-
clearing.
Bit 6, POWER DOWN, deactivates the internal clocks and shuts off the oscillator. Disk
control pins are put in an inactive state. All input signals must be held in a valid state
(D.C. level 1 or 0). POWER DOWN is exited by activating one of the reset functions.
Bit 5, the PDOSC bit, is used to implement crystal oscillator power management. The
internal oscillator in the 82078 can be programmed to be powered either on or off via
PDOSC. This capability is independent of the chip's power-down state. Auto power-
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