3. Theory of Operation
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[603]
893-0040) manufactures custom length cables for these drives for your
application. When interfacing to remote drives, minimize the amount of electrical noise
in the system to avoid corrupting the data transfer between the floppy disk drive and the
floppy disk controller.
STD BUS COMPATIBILITY
The ZT 8954 is fully compatible with both the STD-80 and STD 32 bus specifications.
STD 32 is a superset of STD-80. Both specifications are available through Ziatech.
STD BUS INTERFACE
The ZT 8954 interfaces the STD and STD 32 bus structure to IBM-PC platform floppy
disk controllers. Programmed I/O transfers are used to program the ZT 8954 for a floppy
disk sector read or write. DMA is used for the transfer of floppy disk data. DMA can be
done a byte at a time (which is the IBM PC method); or, with the on-board 16-byte
FIFO, the ZT 8954 can perform block DMA in order to improve bus-latency tolerance.
Under MS-DOS, floppy disk transfers also require the use of an interrupt, which is
nominally jumpered for INTRQ2* on the backplane. The ZT
8954 uses
BUSRQ*/BUSAK* and backplane DMA control signals, by default, for data transfers.
Data Transfers
The floppy disk controller supports both polled and DMA-driven data transfers. Standard
MS-DOS uses DMA, by default, for moving data back and forth between the host CPU's
memory and the floppy disk controller. The DMA transfer is driven by the DMA controller
on board the host CPU board. The ZT 8954 does not have a controller. The BIOS
software is responsible for managing the low-level hardware in DOS systems and in
STD 32 STAR SYSTEM™ multiprocessing applications. All transfers are 8 bits wide.
The normal DMA transfer mechanism is to use BUSRQ* to request a DMA cycle, qualify
DMAIOW* or DMAIOR* with BUSAK* to transfer data, and receive T-C as a terminal
count signal from the host CPU. This is referred to as Mode 2 DMA for the ZT 8954.
Slot-specific DMA, frontplane DMA, and a combination of frontplane and backplane
DMA can also be selected as other modes.
Memory
The ZT 8954 does not occupy or decode any of the STD bus memory address space.
I/O
The ZT 8954 decodes the I/O address range 3F0h-3F7h, with the exception of 3F6h.
Port 3F7h is shared with the hard disk interface (ZT 8952/8953); only one bit is driven
by the ZT 8954 when that port is read by the host CPU. The other seven bits are driven
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