4. FDC Description (82078)
24
Precompensation Delays
PRECOMP
BITS 432
Precompensation
Delay
111
0.00 ns -- DISABLED
001
41.67 ns
010
83.34 ns
011
125.00 ns
100
166.67 ns
101
208.33 ns
110
250.00 ns
000
DEFAULT
Default Precompensation Delays
Data Rate
Precompensation
Delays
1 Mbps
41.67 ns
500 Kbps
125 ns
300 Kbps
125 ns
200 Kbps
125 ns
Main Status Register (MSR)
3F4h Default
The Main Status Register is a read-only register used to control command input and
result output for all commands.
7
6
5
4
3
2
1
0
RQM
DIO
NON
DMA
CMD
BUSY
DRV 3
BUSY
DRV 2
BUSY
DRV 1
BUSY
DRV 0
BUSY
Main Status Register
RQM -- Indicates the host can transfer data if set to logical 1. No access is permitted if
set to logical 0.
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