4. FDC Description (82078)
19
Status Register A (SRA)
3F0h Default
This register is read-only and monitors the state of the interrupt pin and several disk
interface pins. This register is part of the PS/2 register set.
7
6
5
4
3
2
1
0
INT
PENDING
DRV2*
STEP
TRK0* HDSEL
INDX*
WP*
DIR
Status Register A
The INT PENDING bit is used by software to monitor the state of the 82078
INTERRUPT pin. As a read-only register, no default value is associated with a reset
other than that some drive bits change with a reset. The INT PENDING, STEP, HDSEL,
and DIR bits are low after reset.
Status Register B (SRB)
3F1h Default
This register is read-only and monitors the state of several disk interface pins. This
register is part of the PS/2 register set.
7
6
5
4
3
2
1
0
DRIVE
SEL0
1
MOT
WE
WRDATA
TOGGLE
RDDATA
TOGGLE
1
EN1
MOT
EN0
Status Register B
As the only drive input, RDDATA TOGGLE's level always reflects the level as seen on
the cable.
The two TOGGLE bits do not read back the state of their respective pins directly.
Instead, the pins drive a flip-flop which produces a wider and more reliably read pulse.
Bits 6 and 7 are undefined and always return a 1.
After any reset, the activity on the TOGGLE pins is cleared. Drive select and motor
bits are cleared by the RESET pin and not by software resets.
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