4. FDC Description (82078)
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and the FIFO circuits. The DSR Reset clears itself automatically, while the DOR Reset
requires the host to manually clear it. DOR Reset has precedence over the DSR Reset.
The DOR Reset is set automatically upon a pin RESET. You must manually clear this
reset bit in the DOR to exit the reset state.
DMA TRANSFERS
DMA transfers are enabled with the SPECIFY command and are initiated by the 82078
by activating the DRQ pin during a data transfer command. The FIFO is enabled directly
by asserting DACK*.
COMMAND SET/DESCRIPTIONS
Commands can be written whenever the 82078 is in the command phase. Each
command has a unique set of needed parameters and status results. The 82078 checks
to see if the first byte is a valid command and if valid, proceeds with the command.
Refer to the 82078 data sheet for details on the COMMAND SET.
ADDITIONAL INFORMATION
Refer to the Intel
Peripherals Data Book for further details on the 82078-1 Floppy Disk
Controller. When referring to the 82078-1 data sheet, it is important to note that the
ZT 8954 is configured for PS/2 mode through the connection of IDENT1 and IDENT0.
IDENT0 is grounded on the ZT 8954. IDENT1 is tied to Vcc. Also, note that the 82078-1
can be configured for either a 24 MHz crystal/oscillator or a 48 MHz oscillator. The
ZT 8954 uses a 24 MHz crystal for internal timing. The 48 MHz oscillator option is not
provided.
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