Zynq Ult VCU TRD User Guide
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UG1250 (v2019.1) May 29, 2019
Chapter 5:
Hardware Platform
data in 24-bit RGB format and converts it to a 16-bit, 8bpc YUV 4:2:0 output format
using AXI4-Stream. A GPIO is used to reset the subsystem between resolution changes.
• The Video Frame Buffer Write IP uses the same configuration as the one in the TPG and
HDMI RX capture pipelines. It takes YUV 4:2:0 sub-sampled AXI4-Stream input data and
converts it to memory-mapped AXI4 format which is written to memory as 16-bit
packed YUYV. The memory-mapped AXI interface is connected to the HP1 high
performance PS/PL port via an AXI interconnect. For each video frame transfer, an
interrupt is generated. A GPIO is used to reset the IP between resolution changes.
Similar to the TPG and HDMI RX capture pipelines, all the IPs in this pipeline are configured
to transport 2ppc, enabling up to 2160p60 performance.
SDI RX Capture Pipeline
The SDI RX capture pipeline is shown in
.
The serial digital interface (SDI) Receiver Subsystem implements an SDI receive interface in
accordance with the SDI family of standards. The subsystem receives video from a native
SDI interface and generates AXI4-Stream video. The SMPTE UHD-SDI receiver core receives
multiplexed native SDI data streams and generates non-multiplexed 10-bit SDI data
streams in YUV422 format.
The Video Frame Buffer Write IP is used as the Frame Grabber logic, which is designed to
allow efficient and high bandwidth access between AXI4-Streaming Video In interfaces to
X-Ref Target - Figure 5-6
Figure 5-6:
SDI RX Capture Pipeline
32
48
128
128
SDI Rx SS
Frmbuf
Write
Video Timing
AXI-S
AXI-MM
HP1
HPM0/1
AXI-Lite
HP1
PL
PS
SDI Rx Capture Pipeline
32
SDI GT
PHY
VPSS
Scaler
48
Audio
Formatter
48
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