Xilinx Zynq UltraScale+, User Manual

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Zynq Ult VCU TRD User Guide 76
UG1250 (v2019.1) May 29, 2019 www.xilinx.com
Chapter 5: Hardware Platform
Interrupt Map
Table 5-6 shows interrupt ID mapping for the VCU TRD full-fledged design.
Note:
AXI Interrupt Controller used to accommodate all the interrupts as total number of PL-PS
interrupts exceeds 16 in the design.
Table 5-7 shows interrupt ID mapping for VCU audio design.
Table 5-6: Interrupt ID Map for Full-fledged Design
IP Core Interrupt ID
HDMI CTL IIC 94
HDMI Frame Buffer Read 89
HDMI Frame Buffer Write_0 90
HDMI Frame Buffer Write_1 108
HDMI Frame Buffer Write_2 109
HDMI RX 91
HDMI TX 93
Interrupt Controller 107
MIPI Frame Buffer Write 105
MIPI RX SS 104
Sensor IIC 106
TPG Frame Buffer Write 97
VCU 96
Video mixer 95
Video Physical controller 92
HDMI CTL IIC 94
Table 5-7: Interrupt ID Map for VCU Audio Design
IP Core Interrupt ID
HDMI I2C Controller 94
HDMI 1.4/2.0 Transmitter Subsystem v2.0 93
Video Mixer 92
HDMI Frame Buffer Read 89
HDMI Frame Buffer Write 90
HDMI 1.4/2.0 Receiver Subsystem v2.0 91
Audio Formatter MM2S 1 104
Audio Formatter S2MM 1 105
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