Xilinx Zynq UltraScale+, User Manual

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Zynq Ult VCU TRD User Guide 67
UG1250 (v2019.1) May 29, 2019 www.xilinx.com
Chapter 5: Hardware Platform
Ethernet 10G Input/Capture Pipeline
The Ethernet 10G input/capture pipeline is shown in Figure 5-10 .
This pipeline consists of two components, each of them controlled by the APU through an
AXI4-Lite base register interface:
• The 10G/25G high speed Ethernet Subsystem implements the 25G Ethernet MAC with a
physical coding sublayer (PCS) as specified by the 25G Ethernet Consortium. The
156.25 MHz reference clock to the transceiver is provided by the Si570 programmable
oscillator available on the ZCU106 board. For more information, see 10G/25G High
Speed Ethernet Subsystem Product Guide (PG210) [Ref 16] .
• The AXI DMA with enabled scatter gather (SG) mode provides high-bandwidth direct
memory access between memory and the Ethernet 10G Subsystem via AXI
interconnect. For more information, see AXI DMA LogiCORE IP Product Guide (PG021)
[Ref 17] .
X-Ref Target - Figure 5-10
Figure 5-10: Ethernet 10G Input/Capture Pipeline
Ethernet 10G/25G
Subsystem AXI
DMA
HPM0/1
HP1
PL
AXI-Lite AXI-Stream AXI-MM
128
128
32
64
64
Ethernet 10G Input/Capture Pipeline
PS
X21946-120318 X20149-072218 X21946-042519
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