Zynq Ult VCU TRD User Guide
70
UG1250 (v2019.1) May 29, 2019
Chapter 5:
Hardware Platform
HDMI Audio TX Pipeline
This pipeline consists of three main components—Video PHY Controller, HDMI RX
Subsystem, and Audio Formatter, each shared with the audio input/capture pipeline. Refer
to the following sections for more information and for the configuration of each
component:
• Video PHY Controller (see
)
• HDMI RX Subsystem (see
)
• Audio Formatter (see
)
Note:
HDMI RX Subsystem IP is available from Xilinx. HDMI 1.4/2.0 Receiver Subsystem v3.1 is the
current version as of this printing.
Accelerator Processing Pipeline
The accelerator processing pipeline is shown in
. The processing pipeline with a
dummy SDx accelerator is entirely generated by the SDSoC™ tool based on the C code
description. The accelerator function (which is simply copying the input data) is translated
to RTL using the Vivado® tool HLS compiler. The data motion network to transfer video
buffers to and from memory is inferred automatically by SDSoC tool compiler.
The HLS generated accelerator is controlled by an accelerator adaptor that drives all inputs
and captures all outputs. The accelerator adapter has memory-mapped AXI interfaces to
transfer data to and from the HP port and the accelerator. Both HP ports used by the VCU
encoder and decoder are multiplexed with the accelerator adapter. For AXI4-Lite control
interfaces, a HPM port is used.
X-Ref Target - Figure 5-13
Figure 5-13:
Accelerator Processing Pipeline
SDx
Accelerator
(HLS)
HPM0/1
HP2/3
PL
Control
AXI-Lite
AXI-MM
128
128
Accelerator
Adapter
FIFO
PS
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