Zynq Ult VCU TRD User Guide
29
UG1250 (v2019.1) May 29, 2019
Chapter 3:
APU Software Platform
PCIe
PCIe Software
The Xilinx PCI Express DMA (XDMA) IP provides high-performance scatter gather (SG) direct
memory access (DMA) via the Endpoint block for PCI Express. Using this IP and the
associated drivers and software enable you to generate high-throughput PCIe memory
transactions between a host PC and a Xilinx FPGA (see
).
DMA Driver
The purpose of a DMA driver that sits in the host CPU is to prepare for peripheral DMA
transfers, because only the operating system (OS) has full control over the memory system,
the file system, and the user space processes.
Initially the peripheral device’s DMA engine is programmed with the source and destination
addresses of the memory ranges to copy. In a read case, the PCIe Endpoint block driver
running on the client allocates the destination buffer in the client DDR and passes that
address to the host DMA application through userspace registers in the design. When the
destination buffer is ready, the DMA application running on the host starts the DMA engine
by programming the destination address in the DMA registers.
The device is then signaled to begin the DMA transfer, and when the transfer is finished, the
device usually provides interrupts to inform the CPU about completed transfers. For each
X-Ref Target - Figure 3-6
Figure 3-6:
PCI Express DMA (XDMA) IP
M_ARVALID
M_ARREADY
M_ARADDR
...
C2H 0
AXI-MM Read
AXI-MM Write
DMA AXI MM Master
C2H 1
H2C 1
H2C...
C2H...
H2C 0
XDMA
M_RVALID
M_RDATA
M_RREADY
...
M_AWVALID
M_AWREADY
M_AWADDR
...
M_BVALID
M_BRESP
M_BREADY
...
M_AWVALID
M_AWREADY
M_AWADDR
...
X22804-042619
