Xilinx Zynq UltraScale+, User Manual

Page: 72 / 86

Zynq Ult VCU TRD User Guide 72
UG1250 (v2019.1) May 29, 2019 www.xilinx.com
Chapter 5: Hardware Platform
I2S Audio Pipeline
The I2S Transmitter and Receiver cores are soft Xilinx IP cores, which make easy to
implement inter-IC-sound (I2S) interfaces used to connect audio devices for transmitting
and receiving PCM audio. The I2S Transmitter and I2S Receiver cores provide an easy way to
interface the I2S based audio DAC/ADC. These IPs require minimal register programming
and support any audio sampling rates. For more information refer to the I2S Transmitter and
I2S Receiver LogiCORE IP Product Guide (PG308) [Ref 24] .
PL_DDR
The Zynq Ult MPSoC VCU DDR4 Controller is an application-specific DDR
controller that is only supported for use with the Zynq Ult MPSoC VCU
(H.264/H.265 Video Codec unit).
Address Map
Table 5-1 shows the address map for various IP blocks used in PL for the VCU TRD
full-fledged design.
Table 5-1: Address Map for IP Blocks of the VCU TRD Full-fledged Design
IP Core Base Address Offset
AXI Interrupt Controller 0x00A0052000 4K
HDMI I2C Controller 0x00A0050000 4K
MIPI CSI-2 Receiver Subsystem 0x00A00F0000 64K
Sensor I2C Controller 0x00A0051000 4K
Sensor Demosaic 0x00A0250000 64K
HDMI Frame Buffer Read 0x00A0040000 64K
HDMI Frame Buffer Write 0 0x00A0010000 64K
TPG Frame Buffer Write 0x00A00C0000 64K
CSI Frame Buffer Write 0x00A0260000 64K
HDMI Frame Buffer Write 1 0x00A02B0000 64K
HDMI Frame Buffer Write 2 0x00A02C0000 64K
HDMI Frame Buffer Write 3 0x00A0280000 64K
HDMI Frame Buffer Write 4 0x00A0290000 64K
HDMI Frame Buffer Write 5 0x00A02A0000 64K
HDMI Frame Buffer Write 6 0x00A02D0000 64K
Gamma LUT 0x00A0270000 64K
HDMI 1.4/2.0 Receiver Subsystem v2.0 0x00A0000000 64K
Send Feedback