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VCU118 Board User Guide

UG1224 (v1.0) December 15, 2016

www.xilinx.com

Chapter 3:

Board Component Descriptions

Table 3-16:

VCU118 FPGA U1 GTY Transceiver Bank 226 Connections

MGT

Bank

FPGA

(U1)

Pin

FPGA (U1) Pin Name

Schematic Net

Name

Connected Pin

Name

Connected

Device

GTY

Bank

226

AN5

MGTYTXP0_226

PCIE_TX7_P

A47

HSIP(7)

PCIe EDGE Conn.

AN4

MGTYTXN0_226

PCIE_TX7_N

A48

HSIN(7)

AH2

MGTYRXP0_226

PCIE_RX7_P

B45

HSOP(7)

AH1

MGTYRXN0_226

PCIE_RX7_N

B46

HSON(7)

AM7

MGTYTXP1_226

PCIE_TX6_P

A43

HSIP(6)

AM6

MGTYTXN1_226

PCIE_TX6_N

A44

HSIN(6)

AG4

MGTYRXP1_226

PCIE_RX6_P

B41

HSOP(6)

AG3

MGTYRXN1_226

PCIE_RX6_N

B42

HSON(6)

AK7

MGTYTXP2_226

PCIE_TX5_P

A39

HSIP(5)

AK6

MGTYTXN2_226

PCIE_TX5_N

A40

HSIN(5)

AF2

MGTYRXP2_226

PCIE_RX5_P

B37

HSOP(5)

AF1

MGTYRXN2_226

PCIE_RX5_N

B38

HSON(5)

AH7

MGTYTXP3_226

PCIE_TX4_P

A35

HSIP(4)

AH6

MGTYTXN3_226

PCIE_TX4_N

A36

HSIN(4)

AE4

MGTYRXP3_226

PCIE_RX4_P

B33

HSOP(4)

AE3

MGTYRXN3_226

PCIE_RX4_N

B34

HSON(4)

AG9

MGTREFCLK0P_226

MGT226_CLK0_P

(1)

J31

SMA Connectors

J31(P), J30(N)

AG8

MGTREFCLK0N_226

MGT226_CLK0_N

(1)

J30

AE9

MGTREFCLK1P_226

AE8

MGTREFCLK1N_226

BD2

MGTRREF_RS

MGTRREF_226

R1088.1 100

Ω

1% P/U to MGTAVTT_FPGA

BD3

MGTAVTTRCAL_RS

MGTAVTT_FPGA NA

Notes:

1. Ensure that the GTY RefClock being sourced into the RefClock SMAs (J30, J31) is AC coupled for proper clocking operation of

GTY transceivers. Use inline SMA DC blocking capacitors if frequency source output is not AC coupled.

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Summary of Contents for VCU118

Page 1: ...VCU118 Evaluation Board User Guide UG1224 v1 0 December 15 2016...

Page 2: ...User Guide 2 UG1224 v1 0 December 15 2016 www xilinx com Revision History The following table shows the revision history for this document Date Version Revision 12 15 2016 1 0 Initial Xilinx release S...

Page 3: ...15 Installing the VCU118 Board in a PC Chassis 16 FPGA Configuration 17 Chapter 3 Board Component Descriptions Overview 19 Component Descriptions 19 Virtex UltraScale XCVU9P L2FLGA2104 Device 19 DDR4...

Page 4: ...oard Power System 106 FMC VADJ_1V8 Power Rail 108 Monitoring Voltage and Current 108 Cooling Fan 110 System Controller 111 Configuration Options 112 Appendix A VITA 57 1 and 57 4 FMC Connector Pinouts...

Page 5: ...ng DDR4 and RLD3 component memory Dual small form factor pluggable QSFP connector Sixteen lane PCI Express interface Ethernet PHY General purpose I O Two UART interfaces FireFly Optical x4 28 G connec...

Page 6: ...ecember 15 2016 www xilinx com Chapter 1 Introduction Block Diagram A block diagram of the VCU118 evaluation board is shown in Figure 1 1 X Ref Target Figure 1 1 Figure 1 1 VCU118 Evaluation Board Blo...

Page 7: ...h separate micro B USB connector Clock sources Si5335A quad clock generator Three Si570 I2C programmable LVDS clock generators One SG5032 fixed 250 MHz LVDS clock generator Si5328B clock multiplier an...

Page 8: ...alog to digital front end Configuration options BPI linear flash memory Digilent USB configuration module Platform cable USB II interface 2x7 2 mm connector Board Specifications Dimensions Height 6 92...

Page 9: ...VCU118 Board User Guide 9 UG1224 v1 0 December 15 2016 www xilinx com Chapter 1 Introduction Operating Voltage 12 VDC Send Feedback...

Page 10: ...Table 2 1 Table 2 1 identifies the components references the respective schematic page numbers and links to a detailed functional description of the components and board features in Chapter 3 IMPORTAN...

Page 11: ...2 102616 Table 2 1 VCU118 Board Component Descriptions Callout Feature Notes Schematic Page Number 1 Virtex UltraScale XCVU9P L2FLGA2104 Device with fan sink on soldered FPGA XCVU9P L2FLGA2104E Cofan...

Page 12: ...grammable user clock Si570_2 I2C programmable user clock 3 3V LVDS U38 Silicon Labs SI570BAB0000544DG default 156 250 MHz 45 14 250 MHz Clock fixed SG5032 250 MHz user clock 3 3V LVDS U14 bottom with...

Page 13: ...and Current power management voltage and current sensing TI Current and Power Monitor INA226AIDGS 60 67 33 GTY Transceivers FMCP HSPC connector J22 Samtec ASP_184329_01 34 38 34 FMC HPC1 Connector J2...

Page 14: ...2 2 Default Switch Settings Switch Function Default Comments Figure 2 1 Callout Schematic Page SW1 SPST slide switch OFF Board shipped with power switch off 30 59 SW12 4 pole GPIO 0000 Positions 1 4...

Page 15: ...re 2 2 VCU118 Board Header Jumper Locations 8 6 5 7 3 1 4 2 X18026 100416 Table 2 3 Default Jumper Settings Jumper Function Default Comments Figure 2 2 Callout Schematic Page J5 Power on reset POR ove...

Page 16: ...he VCU118 board remove the six screws retaining the six rubber feet with their standoffs and the PCIe bracket Reinstall the PCIe bracket using two of the previously removed screws 2 Power down the hos...

Page 17: ...he 4 pin adapter cable connector CAUTION Do NOT plug a PC ATX power supply 6 pin connector into J15 on the VCU118 evaluation board The ATX 6 pin connector has a different pin out than J15 Connecting a...

Page 18: ...Setup and Configuration For complete details on configuring the FPGA see UltraScale Architecture Configuration User Guide UG570 Ref 2 Figure 2 4 shows the configuration mode DIP switch SW16 default s...

Page 19: ...ctive schematic page numbers and links to the corresponding detailed functional description in this chapter Component locations are shown in Figure 2 1 page 11 Component Descriptions Virtex UltraScale...

Page 20: ...geable 1 5V lithium button type battery B1 is soldered to the board with the positive output connected to the XCVU9P device U1 VBATT pin AT11 The battery supply current IBATT specification is 150 nA m...

Page 21: ...Bank Power Supply Rail Net Name Voltage Bank 0 VCC1V8_FPGA 1 8V HP Bank 40 VCC1V2_FPGA 1 2V HP Bank 41 VCC1V2_FPGA 1 2V HP Bank 42 VCC1V2_FPGA 1 2V HP Bank 43 VADJ_1V8_FPGA 1 8V HP Bank 45 VADJ_1V8_FP...

Page 22: ...Memory 80 bit I F C1 to FPGA U1 Banks 71 72 and 73 FPGA U1 Pin Schematic Net Name I O Standard Component Memory Pin Pin Name Ref Des F11 DDR4_C1_DQ0 POD12_DCI G2 DQL0 U60 E11 DDR4_C1_DQ1 POD12_DCI F7...

Page 23: ...I G3 DQSL_T U61 J19 DDR4_C1_DQS2_C DIFF_POD12_DCI F3 DQSL_C U61 F16 DDR4_C1_DQS3_T DIFF_POD12_DCI B7 DQSU_T U61 E16 DDR4_C1_DQS3_C DIFF_POD12_DCI A7 DQSU_C U61 K17 DDR4_C1_DM2 POD12_DCI E7 DML_B DBIL_...

Page 24: ...4_C1_DQ54 POD12_DCI J3 DQL6 U63 J22 DDR4_C1_DQ55 POD12_DCI J7 DQL7 U63 H23 DDR4_C1_DQ56 POD12_DCI A3 DQU0 U63 H22 DDR4_C1_DQ57 POD12_DCI B8 DQU1 U63 E23 DDR4_C1_DQ58 POD12_DCI C3 DQU2 U63 E22 DDR4_C1_...

Page 25: ...I B7 DQSU_T U64 A8 DDR4_C1_DQS9_C DIFF_POD12_DCI A7 DQSU_C U64 E24 DDR4_C1_DM8 POD12_DCI E7 DML_B DBIL_B U64 C9 DDR4_C1_DM9 POD12_DCI E2 DMU_B DBIU_B U64 D14 DDR4_C1_A0 SSTL12_DCI P3 A0 U60 U64 B15 DD...

Page 26: ...CS_B SSTL12_DCI L7 CS_B U60 U64 R17 DDR4_C1_ALERT_B SSTL12_DCI P9 ALERT_B U60 U64 N20 DDR4_C1_RESET_B LVCMOS12 P1 RESET_B U60 U64 A20 DDR4_C1_TEN SSTL12_DCI N9 TEN U60 U64 Table 3 2 DDR4 Memory 80 bit...

Page 27: ...2_DQ21 POD12_DCI H8 DQL5 U136 AU31 DDR4_C2_DQ22 POD12_DCI J3 DQL6 U136 AV31 DDR4_C2_DQ23 POD12_DCI J7 DQL7 U136 AR33 DDR4_C2_DQ24 POD12_DCI A3 DQU0 U136 AT34 DDR4_C2_DQ25 POD12_DCI B8 DQU1 U136 AT29 D...

Page 28: ...D12_DCI F3 DQSL_C U137 BE39 DDR4_C2_DQS5_T DIFF_POD12_DCI B7 DQSU_T U137 BF39 DDR4_C2_DQS5_C DIFF_POD12_DCI A7 DQSU_C U137 BC34 DDR4_C2_DM4 POD12_DCI E7 DML_B DBIL_B U137 BE40 DDR4_C2_DM5 POD12_DCI E2...

Page 29: ...71 POD12_DCI J7 DQL7 U139 BC25 DDR4_C2_DQ72 POD12_DCI A3 DQU0 U139 BC26 DDR4_C2_DQ73 POD12_DCI B8 DQU1 U139 BB28 DDR4_C2_DQ74 POD12_DCI C3 DQU2 U139 BC28 DDR4_C2_DQ75 POD12_DCI C7 DQU3 U139 AY27 DDR4_...

Page 30: ...C2_A9 SSTL12_DCI R7 A9 U135 U139 AR28 DDR4_C2_A10 SSTL12_DCI M3 A10 AP U135 U139 AR27 DDR4_C2_A11 SSTL12_DCI T2 A11 U135 U139 AV25 DDR4_C2_A12 SSTL12_DCI M7 A12 BC_B U135 U139 AT25 DDR4_C2_A13 SSTL12_...

Page 31: ...matic Net Name I O Standard Component Memory Pin Pin Name Ref Des H39 RLD3_C3_72B_DQ0 SSTL12 D11 DQ0 U141 H40 RLD3_C3_72B_DQ1 SSTL12 E10 DQ1 U141 G40 RLD3_C3_72B_DQ2 SSTL12 C8 DQ2 U141 F40 RLD3_C3_72B...

Page 32: ...QK0 U141 J40 RLD3_C3_72B_QK0_N DIFF_SSTL12 E8 QK0_B U141 F34 RLD3_C3_72B_QK1_P DIFF_SSTL12 K9 QK1 U141 E34 RLD3_C3_72B_QK1_N DIFF_SSTL12 J8 QK1_B U141 E39 RLD3_C3_72B_QK2_P DIFF_SSTL12 D5 QK2 U141 D39...

Page 33: ...SSTL12 B3 DQ24 U142 E27 RLD3_C3_72B_DQ61 SSTL12 A6 DQ25 U142 G25 RLD3_C3_72B_DQ62 SSTL12 A4 DQ26 U142 B28 RLD3_C3_72B_DQ63 SSTL12 J4 DQ27 U142 A28 RLD3_C3_72B_DQ64 SSTL12 K3 DQ28 U142 C27 RLD3_C3_72B...

Page 34: ...TL12 H13 A10 U141 U142 C33 RLD3_C3_72B_A11 SSTL12 D1 A11 U141 U142 C32 RLD3_C3_72B_A12 SSTL12 H11 A12 U141 U142 D30 RLD3_C3_72B_A13 SSTL12 D13 A13 U141 U142 E29 RLD3_C3_72B_A14 SSTL12 H3 A14 U141 U142...

Page 35: ...sources UG571 Ref 3 For more details about the Micron RLD3 component memory see the Micron MT44K32M36RB 083E Data Sheet Ref 18 L29 RLD3_C3_72B_RESET_B SSTL12 A13 RESET_B U141 U142 N29 RLD3_C3_72B_CS_B...

Page 36: ...l 90 MHz oscillator connected to the FPGA bank 65 EMCCLK pin AL20 By default UltraScale FPGAs use the parallel NOR flash asynchronous read in the master BPI configuration mode A full XCVU9P 641 272 86...

Page 37: ...8 Board User Guide 37 UG1224 v1 0 December 15 2016 www xilinx com Chapter 3 Board Component Descriptions X Ref Target Figure 3 2 Figure 3 2 Linear BPI 128 MB 1 Gbit Flash Memory X18006 100416 Send Fee...

Page 38: ...1 DQ8 AN18 BPI_FLASH_D9 LVCMOS18 E3 DQ9 AR18 BPI_FLASH_D10 LVCMOS18 F3 DQ10 AR17 BPI_FLASH_D11 LVCMOS18 F4 DQ11 AT20 BPI_FLASH_D12 LVCMOS18 F5 DQ12 AT19 BPI_FLASH_D13 LVCMOS18 H5 DQ13 AT17 BPI_FLASH_D...

Page 39: ...ystem controller access to general purpose nonvolatile micro SD memory cards and peripherals The micro SD card slot is designed to support 50 MHz high speed micro SD cards BB18 BPI_FLASH_A16 LVCMOS18...

Page 40: ...ration takes priority over the configuration method selected through the FPGA mode pins M 2 0 wired to SW16 positions 2 4 The JTAG chain of the VCU118 board is illustrated in Figure 3 3 For more detai...

Page 41: ...software debugger to access the FPGA The Xilinx tools can also program the BPI parallel flash memory Clock Generation Figure 2 1 callout 10 The VCU118 evaluation board provides multiple clock sources...

Page 42: ...118 Clock Sources to XCVU9P FPGA U1 Connections Clock Source Device U Pin Schematic Net Name I O Standard FPGA U1 Pin SI53340 U157 9 SYSCLK1_300_P LVDS G31 SI53340 U157 10 SYSCLK1_300_N LVDS F31 SI533...

Page 43: ...pair USER_SI570_CLOCK1_P N connected to XCVU9P FPGA U1 bank 64 global clock GC pins AW23 and AW22 respectively U157 output Q3 is not connected Clock generator U122 Silicon Labs SI5335A B03426 GM CLK0A...

Page 44: ...put select pin 2 is wired to 2 pin header J8 and a pull down resistor The default J8 setting is jumper OFF which allows the pull down resistor to select U157 input CLK0 the SI5335A quad clock generato...

Page 45: ...dedicated EMCCLK input pin AL20 Output CLK3 33 3333 MHz single ended 1 8V LVCMOS series resistor coupled SYSCTLR_CLK connected to system controller Programmable User Clock 1 Figure 2 1 callout 12 The...

Page 46: ...he U104 select signal High and selecting the U104 CLK1 input On power up the U32 SI570 user clock defaults to an output frequency of 156 250 MHz The system controller and user applications can change...

Page 47: ...I570 user clock defaults to an output frequency of 156 250 MHz The Zynq 7000 AP SoC system controller or FPGA user IP can change the output frequency within the range of 10 MHz to 810 MHz through an I...

Page 48: ...Q0 drives clock pair 250MHZ_CLK1_P N connected to XCVU9P FPGA U1 HP bank 71 GC pins E12 and D12 respectively U21 output Q1 drives clock pair 250MHZ_CLK2_P N connected to XCVU9P FPGA U1 HP bank 41 GC p...

Page 49: ...J35 signal USER_SMA_CLOCK_N connected to U1 HP bank 45 GC pin P32 Bank 45 VADJ_1V8_FPGA VCCO is nominally 1 8V The USER_SMA_CLOCK input voltage swing should not exceed the voltage setting on the VADJ...

Page 50: ...er attenuated clock SI5328_CLOCK2_C_P U57 output pin 35 SI5328_CLOCK2_C_N U57 output pin 34 is routed as a reference clock to FPGA U1 GTY Quad 232 inputs MGTREFCLK1P U1 pin N9 and MGTREFCLK1N U1 pin N...

Page 51: ...tive Low input at U57 pin 1 RST_B performs an external hardware reset of this device This resets all internal logic to a known state and forces the device registers to their default value The clock ou...

Page 52: ...the GTY transceivers are wired to the PCIe 16 lane edge connector U2 Twenty four of the GTY transceivers are wired to FMC HSPC connector J22 The reference clock for a quad can be sourced from the quad...

Page 53: ..._3_M2C_C_P N U39 Four GTY transceivers allocated to FMC HSPC DP 12 15 J22 Quad 126 MGTREFCLK0 FMCP_HSPC_GBT0_1_M2C_C_P N U40 MGTREFCLK1 FMCP_HSPC_GBT1_1_M2C_C_P N U39 Four GTY transceivers allocated t...

Page 54: ...21_C2M_P Y6 DP21_C2M_P BB43 MGTYTXN1_120 FMCP_HSPC_DP21_C2M_N Y7 DP21_C2M_N BA45 MGTYRXP1_120 FMCP_HSPC_DP21_M2C_P M10 DP21_M2C_P BA46 MGTYRXN1_120 FMCP_HSPC_DP21_M2C_N M11 DP21_M2C_N AY42 MGTYTXP2_12...

Page 55: ...P1_M2C_P A2 DP1_M2C_P AN46 MGTYRXN1_121 FMCP_HSPC_DP1_M2C_N A3 DP1_M2C_N AM42 MGTYTXP2_121 FMCP_HSPC_DP2_C2M_P A26 DP2_C2M_P AM43 MGTYTXN2_121 FMCP_HSPC_DP2_C2M_N A27 DP2_C2M_N AL45 MGTYRXP2_121 FMCP_...

Page 56: ...P9_C2M_N AF43 MGTYRXP1_122 FMCP_HSPC_DP9_M2C_P B4 DP9_M2C_P AF44 MGTYRXN1_122 FMCP_HSPC_DP9_M2C_N B5 DP9_M2C_N AG40 MGTYTXP2_122 FMCP_HSPC_DP10_C2M_P Z24 DP10_C2M_P AG41 MGTYTXN2_122 FMCP_HSPC_DP10_C2...

Page 57: ...Y31 DP13_C2M_N AB43 MGTYRXP1_125 FMCP_HSPC_DP13_M2C_P Z16 DP13_M2C_P AB44 MGTYRXN1_125 FMCP_HSPC_DP13_M2C_N Z17 DP13_M2C_N W40 MGTYTXP2_125 FMCP_HSPC_DP14_C2M_P M18 DP14_C2M_P W41 MGTYTXN2_125 FMCP_H...

Page 58: ...C_DP5_M2C_P A18 DP5_M2C_P U46 MGTYRXN1_126 FMCP_HSPC_DP5_M2C_N A19 DP5_M2C_N M42 MGTYTXP2_126 FMCP_HSPC_DP6_C2M_P B36 DP6_C2M_P M43 MGTYTXN2_126 FMCP_HSPC_DP6_C2M_N B37 DP6_C2M_N R45 MGTYRXP2_126 FMCP...

Page 59: ...M31 DP17_C2M_N J45 MGTYRXP1_127 FMCP_HSPC_DP17_M2C_P Y34 DP17_M2C_P J46 MGTYRXN1_127 FMCP_HSPC_DP17_M2C_N Y35 DP17_M2C_N D42 MGTYTXP2_127 FMCP_HSPC_DP18_C2M_P M34 DP18_C2M_P D43 MGTYTXN2_127 FMCP_HSP...

Page 60: ...70_CLOCK1_C_P N U104 Four GTY transceivers allocated to PCIe lanes 11 8 Quad 226 MGTREFCLK0 MGT226_CLK0_P N SMA J31 P J30 N MGTREFCLK1 not connected Four GTY transceivers allocated to PCIe lanes 7 4 Q...

Page 61: ...XP0_224 PCIE_TX15_P A80 HSIP 15 PCIe EDGE Conn U2 BE4 MGTYTXN0_224 PCIE_TX15_N A81 HSIN 15 BB2 MGTYRXP0_224 PCIE_RX15_P B78 HSOP 15 BB1 MGTYRXN0_224 PCIE_RX15_N B79 HSON 15 BC5 MGTYTXP1_224 PCIE_TX14_...

Page 62: ...E_TX10_P A60 HSIP 10 AT6 MGTYTXN1_225 PCIE_TX10_N A61 HSIN 10 AM2 MGTYRXP1_225 PCIE_RX10_P B58 HSOP 10 AM1 MGTYRXN1_225 PCIE_RX10_N B59 HSON 10 AR5 MGTYTXP2_225 PCIE_TX9_P A56 HSIP 9 AR4 MGTYTXN2_225...

Page 63: ...ON 6 AK7 MGTYTXP2_226 PCIE_TX5_P A39 HSIP 5 AK6 MGTYTXN2_226 PCIE_TX5_N A40 HSIN 5 AF2 MGTYRXP2_226 PCIE_RX5_P B37 HSOP 5 AF1 MGTYRXN2_226 PCIE_RX5_N B38 HSON 5 AH7 MGTYTXP3_226 PCIE_TX4_P A35 HSIP 4...

Page 64: ...IE_RX3_N B28 HSIP 3 AD7 MGTYTXP1_227 PCIE_TX2_P A25 HSIN 2 AD6 MGTYTXN1_227 PCIE_TX2_N A26 HSIP 2 AC4 MGTYRXP1_227 PCIE_RX2_P B23 HSIN 2 AC3 MGTYRXN1_227 PCIE_RX2_N B24 HSIP 2 AB7 MGTYTXP2_227 PCIE_TX...

Page 65: ...N W4 MGTYRXP1_231 QSFP1_RX2_P 22 RX2P W3 MGTYRXN1_231 QSFP1_RX2_N 21 RX2N P7 MGTYTXP2_231 QSFP1_TX3_P 33 TX3P P6 MGTYTXN2_231 QSFP1_TX3_N 34 TX3N V2 MGTYRXP2_231 QSFP1_RX3_P 14 RX3P V1 MGTYRXN2_231 QS...

Page 66: ...2_TX2_P 3 TX2P K6 MGTYTXN1_232 QSFP2_TX2_N 2 TX2N R4 MGTYRXP1_232 QSFP2_RX2_P 22 RX2P R3 MGTYRXN1_232 QSFP2_RX2_N 21 RX2N J5 MGTYTXP2_232 QSFP2_TX3_P 33 TX3P J4 MGTYTXN2_232 QSFP2_TX3_N 34 TX3N P2 MGT...

Page 67: ...RX1_P B17 RX1P K1 MGTYRXN0_233 FIREFLY_RX1_N B18 RX1N F7 MGTYTXP1_233 FIREFLY_TX2_P B3 TX2P F6 MGTYTXN1_233 FIREFLY_TX2_N B2 TX2N H2 MGTYRXP1_233 FIREFLY_RX2_P A17 RX2P H1 MGTYRXN1_233 FIREFLY_RX2_N A...

Page 68: ...clock input is from the U2 edge connector It is AC coupled to FPGA U1 through the MGTREFCLK0 pins of Quad 225 PCIE_CLK_Q0_P is connected to U1 pin AL9 and the _N net is connected to pin AL8 The PCI E...

Page 69: ...t Figure 3 12 Figure 3 12 PCI Express Lane Size Select Jumper J7 X17997 100416 Table 3 21 VCU118 Board FPGA U1 to PCIe Edge U2 Connections FPGA U1 Pin FPGA U1 Pin Name Schematic Net Name PCIe Edge U2...

Page 70: ...TYTXP3_224 PCIE_TX12_P A68 HSIP 12 AW4 MGTYTXN3_224 PCIE_TX12_N A69 HSIN 12 BA5 MGTYTXP2_224 PCIE_TX13_P A72 HSIP 13 BA4 MGTYTXN2_224 PCIE_TX13_N A73 HSIN 13 BC5 MGTYTXP1_224 PCIE_TX14_P A76 HSIP 14 B...

Page 71: ..._225 PCIE_RX8_P B50 HSOP 8 AJ3 MGTYRXN3_225 PCIE_RX8_N B51 HSON 8 AK2 MGTYRXP2_225 PCIE_RX9_P B54 HSOP 9 AK1 MGTYRXN2_225 PCIE_RX9_N B55 HSON 9 AM2 MGTYRXP1_225 PCIE_RX10_P B58 HSOP 10 AM1 MGTYRXN1_22...

Page 72: ...rd contains two quad 4 channel small form factor pluggable 28 Gb s QSFP connectors QSFP1 U145 and QSFP2 U123 which accept 28 Gb s QSFP optical modules Each connector is housed within a single 28 Gb s...

Page 73: ...7 MGTYTXP2_231 QSFP1_TX3_P Output 33 TX3P P6 MGTYTXN2_231 QSFP1_TX3_N Output 34 TX3N V2 MGTYRXP2_231 QSFP1_RX3_P Input 14 RX3P V1 MGTYRXN2_231 QSFP1_RX3_N Input 15 RX3N M7 MGTYTXP3_231 QSFP1_TX4_P Out...

Page 74: ...nput 15 RX3N H7 MGTYTXP3_232 QSFP2_TX4_P Output 6 TX4P H6 MGTYTXN3_232 QSFP2_TX4_N Output 5 TX4N M2 MGTYRXP3_232 QSFP2_RX4_P Input 25 RX4P M1 MGTYRXN3_232 QSFP2_RX4_N Input 24 RX4N U28 11 SC3 QSFP2_II...

Page 75: ...stem is a two part connector designed for applications up to 28 Gb s It is based on two connectors a micro high speed edge connector UEC5 Series shown rear left with two rows of 19 positions providing...

Page 76: ...6 UG1224 v1 0 December 15 2016 www xilinx com Chapter 3 Board Component Descriptions Figure 3 15 shows the schematic representation X Ref Target Figure 3 15 Figure 3 15 FireFly Connector Schematic X17...

Page 77: ...t A18 RX2N E5 MGTYTXP2_233 FIREFLY_TX3_P Output A6 TX3P E4 MGTYTXN2_233 FIREFLY_TX3_N Output A5 TX3N F2 MGTYRXP2_233 FIREFLY_RX3_P Input B14 RX3P F1 MGTYRXN2_233 FIREFLY_RX3_N Input B15 RX3N C5 MGTYTX...

Page 78: ...ode with PHY address 4 0 00011 Table 3 25 lists the FPGA U1 to U7 DP83867ISRGZ Ethernet PHY connections Table 3 25 FPGA U1 to Ethernet PHY U7 Connections FPGA U1 Pin Net Name I O Standard DP83867ISRGZ...

Page 79: ...s are visible within the frame of the RJ45 Ethernet jack as shown in Figure 3 16 As viewed from the front opening the left green LED is the link activity indicator the right green LED is the 1000BASE...

Page 80: ...P U1 FPGA UART2 ECI 2 wire interface is connected to the system controller Silicon Labs provides royalty free virtual COM port VCP drivers for the host computer These drivers permit the CP2105GM dual...

Page 81: ...V8_FPGA and system controller are wired to the same IIC_MAIN_SDA SCL I C bus The common I C bus is then routed to a pair of 1 to 8 channel TI TCA9548 bus switches U28 address 0x74 and U80 address 0x75...

Page 82: ...ABLE_B PMBUS_ALERT MAXIM_CABLE_B PMBUS_ALERT UTIL_3V3 to VCC1V2_FPGA Q27 IIC MUX1 TCA9548 PMBUS FMCP_HSPC FMC_HPC1 EEPROM 0x75 0x11 0x1B 0x70 0x73 0xx 0xx 0x50 IIC MUX1 TCA9548 0x74 SI570 x1 NC QSFPI...

Page 83: ...KX U164 U165 U166 FMCP HSPC FMC Plus 1 0bXXXXX00 0x J22 FMCP HSPC FMC HPC1 2 0bXXXXX00 0x J2 FMC HPC I2C EEPROM 3 0b1010000 0x50 U12 M24C08 PMBus INA226AIDGS power monitor 4 0b0010000 0 b1001000 0x40...

Page 84: ...n DS25 MGTVCCAUX On DS26 12V On DS27 SYS_2V5 On DS28 SYS_1V8 On DS31 GPIO_LED_7 DS32 GPIO_LED_6 DS33 GPIO_LED_5 DS34 FPGA done DS36 DDR4 C1 VTT On DS40 SYS_5V0 On DS42 SYSCTLR INIT DS43 SYSCTLR status...

Page 85: ...abilities Eight user LEDs callout 24 GPIO_LED 7 0 DS31 DS32 DS33 DS10 DS19 DS8 DS6 DS7 Five user pushbuttons and CPU reset switch callout 25 GPIO_SW NESWC SW10 SW9 SW8 SW6 SW7 CPU_RESET SW5 callout 25...

Page 86: ...December 15 2016 www xilinx com Chapter 3 Board Component Descriptions User Pushbuttons Figure 2 1 callout 25 Figure 3 20 shows the user pushbuttons circuit X Ref Target Figure 3 20 Figure 3 20 User P...

Page 87: ...Pushbutton Figure 2 1 callout 25 Figure 3 21 shows the CPU reset pushbutton circuit GPIO DIP Switch Figure 2 1 callout 26 Figure 3 22 shows the GPIO DIP switch circuit X Ref Target Figure 3 21 Figure...

Page 88: ...42 AV36 GPIO_LED_6 Output LVCMOS12 DS13 BANK 42 BA37 GPIO_LED_7 Output LVCMOS12 DS18 Directional pushbuttons Active High are wired in parallel to FPGA BANK 64 and system controller U111 Bank 501 BANK...

Page 89: ...IO headers J52 and J53 The Pmod nets connected to these headers are accessed using level shifters U41 PMOD0 J52 and U42 PMOD1 J53 The level shifters are wired to XCVU9P FPGA U1 banks 47 and 67 Figure...

Page 90: ...PMOD0_1 J52 3 AW15 PMOD0_2_LS LVCMOS18 U41 5 U41 16 PMOD0_2 J52 5 AV15 PMOD0_3_LS LVCMOS18 U41 6 U41 15 PMOD0_3 J52 7 AV16 PMOD0_4_LS LVCMOS18 U41 7 U41 14 PMOD0_4 J52 2 AU16 PMOD0_5_LS LVCMOS18 U41...

Page 91: ...Sliding the switch actuator from the off to on position applies 12VDC power from the 6 pin mini fit power input connector J15 Green LED DS20 illuminates when power is available at the VCU118 power con...

Page 92: ...pin peripheral connector The Xilinx part number for this cable is 2600304 and is equivalent to the Sourcegate Technologies part number AZCBL WH 1109 RA4 See Ref 29 for ordering information Figure 3 25...

Page 93: ...ine card FMC specification by providing a subset implementation of the high pin count connector at J2 HPC1 HPC connectors use a 10 x 40 form factor populated with 400 pins The connector is keyed so th...

Page 94: ...defined by the FMC specification see Appendix A VITA 57 1 and 57 4 FMC Connector Pinouts provides connectivity for up to 160 single ended or 80 differential user defined signals 10 transceiver differe...

Page 95: ..._LA10_P LVDS BB13 D12 FMC_HPC1_LA05_N LVDS BF14 C15 FMC_HPC1_LA10_N LVDS BB12 D14 FMC_HPC1_LA09_P LVDS BA14 C18 FMC_HPC1_LA14_P LVDS AW7 D15 FMC_HPC1_LA09_N LVDS BB14 C19 FMC_HPC1_LA14_N LVDS BB16 D17...

Page 96: ...P LVDS AV9 H16 FMC_HPC1_LA11_P LVDS BA16 G19 FMC_HPC1_LA16_N LVDS AV8 H17 FMC_HPC1_LA11_N LVDS BA15 G21 FMC_HPC1_LA20_P LVDS AW11 H19 FMC_HPC1_LA15_P LVDS BB16 G22 FMC_HPC1_LA20_N LVDS AY10 H20 FMC_HP...

Page 97: ...1V8_FPGA voltage regulator PGOOD level shifted by U44 2 FPGA U1 JTAG TCK TMS pins AE13 AF15 are buffered by U19 SN74AVC8T245 3 J2 HPC1 TDO TDI connections to U132 HPC1 FMC JTAG bypass switch N C norma...

Page 98: ...by the FMC specification see Appendix A VITA 57 1 and 57 4 FMC Connector Pinouts provides connectivity for up to 160 single ended or 80 differential user defined signals 24 transceiver differential pa...

Page 99: ..._P LVDS N45 A14 FMCP_HSPC_DP4_M2C_P LVDS W45 B13 FMCP_HSPC_DP7_M2C_N LVDS N46 A15 FMCP_HSPC_DP4_M2C_N LVDS W46 B16 FMCP_HSPC_DP6_M2C_P LVDS R45 A18 FMCP_HSPC_DP5_M2C_P LVDS U45 B17 FMCP_HSPC_DP6_M2C_N...

Page 100: ...31 D15 FMCP_HSPC_LA09_N LVDS AK33 C19 FMCP_HSPC_LA14_N LVDS AH31 D17 FMCP_HSPC_LA13_P LVDS AJ35 C22 FMCP_HSPC_LA18_CC_P LVDS R31 D18 FMCP_HSPC_LA13_N LVDS AJ36 C23 FMCP_HSPC_LA18_CC_N LVDS P31 D20 FMC...

Page 101: ...LVDS T16 E15 FMCP_HSPC_HA16_P LVDS T14 F14 FMCP_HSPC_HA12_N LVDS T15 E16 FMCP_HSPC_HA16_N LVDS R13 F16 FMCP_HSPC_HA15_P LVDS M13 E18 FMCP_HSPC_HA20_P LVDS M15 F17 FMCP_HSPC_HA15_N LVDS M12 E19 FMCP_H...

Page 102: ...C_LA16_N LVDS AH35 H17 FMCP_HSPC_LA11_N LVDS AJ31 G21 FMCP_HSPC_LA20_P LVDS N32 H19 FMCP_HSPC_LA15_P LVDS AG32 G22 FMCP_HSPC_LA20_N LVDS M32 H20 FMCP_HSPC_LA15_N LVDS AG33 G24 FMCP_HSPC_LA22_P LVDS N3...

Page 103: ..._HSPC_HA14_N LVDS L11 K16 FMCP_HSPC_HA17_CC_P LVDS R11 J18 FMCP_HSPC_HA18_P LVDS P15 K17 FMCP_HSPC_HA17_CC_N LVDS P11 J19 FMCP_HSPC_HA18_N LVDS N15 K19 FMCP_HSPC_HA21_P LVDS K14 J21 FMCP_HSPC_HA22_P L...

Page 104: ..._HSPC_SYNC_C2M_N LVDS AN35 M18 FMCP_HSPC_DP14_C2M_P LVDS W40 L20 FMCP_HSPC_REFCLK_C2M_P LVDS AN33 M19 FMCP_HSPC_DP14_C2M_N LVDS W41 L21 FMCP_HSPC_REFCLK_C2M_N LVDS AP33 M22 FMCP_HSPC_DP15_C2M_P LVDS U...

Page 105: ..._DP13_M2C_N LVDS AB44 Y19 FMCP_HSPC_DP14_M2C_N LVDS AA46 Z20 FMCP_HSPC_GBTCLK5_M2C_P LVDS AN40 Y22 FMCP_HSPC_DP15_M2C_P LVDS Y43 Z21 FMCP_HSPC_GBTCLK5_M2C_N LVDS AN41 Y23 FMCP_HSPC_DP15_M2C_N LVDS Y44...

Page 106: ...Board Component Descriptions VCU118 Board Power System Figure 2 1 callout 31 The VCU118 hosts a Maxim PMBus based power system Figure 3 27 shows the VCU118 power system block diagram X Ref Target Figu...

Page 107: ...l POL controller 10A VADJ_1V8_FPGA 1 80V MAX15301 U6 0x15 Maxim InTune digital POL controller 10A VCCINTIO_BRAM_FPGA 0 85V MAX15301 U4 0x14 Maxim InTune digital POL controller 10A VCC1V2_FPGA 1 20V MA...

Page 108: ...ards are attached with differing VADJ requirements VADJ_1V8 is set to the lowest value compatible with the VCU118 board and the FMC modules within the available choices of 1 2V 1 5V 1 8V and 0 0V If n...

Page 109: ...J_1V8_FPGA MAX15301 U30 1 80 10 0x12 U27 0X42 64 VCCINTIO_BRAM_FPGA MAX15301 U6 0 85 10 0x15 U8 0x48 65 VCC1V2_FPGA MAX15301 U4 1 20 10 0x14 U29 0x43 66 MGTAVCC_FPGA MAX20751 U166 0 90 17 0x72 U37 0x4...

Page 110: ...U118 fan circuit uses a Maxim MAX6643 fan controller that autonomously monitors the FPGA die temperature pins DXP and DXN The fan circuit is set up to increase fan speed as the FPGA temperature increa...

Page 111: ...h as clocks FMC functionality and power systems The VCU118 website also includes a VCU118 System Controller Tutorial XTP447 Ref 14 and VCU118 Software Install and Board Setup Tutorial XTP449 Ref 15 A...

Page 112: ...supports two of the seven UltraScale FPGA configuration modes Master BPI using the onboard linear BPI flash memory JTAG using USB JTAG configuration port Digilent module U115 Xilinx platform cable 2...

Page 113: ...cludes a system controller enable switch in position 1 To obtain the fastest configuration speed an external 90 MHz clock from the Silicon Labs Si5335A U122 is wired to the EMCCLK pin of the FPGA on b...

Page 114: ...view Figure A 1 shows the pinout of the FPGA mezzanine card FMC high pin count HPC J2 defined by the VITA 57 1 FMC specification For a description of how the VCU118 evaluation board implements the FMC...

Page 115: ...Figure A 2 shows the pinout of the FPGA mezzanine card plus FMCP connector J22 defined by the VITA 57 4 FMC specification For a description of how the VCU118 evaluation board implements the FMC speci...

Page 116: ...the constraint files generated by tools such as the memory interface generator MIG and base system builder BSB The FMC connectors J22 FMCP and J2 FMC HPC1 are connected to 1 8V VADJ banks Because dif...

Page 117: ...get_ports 250MHZ_CLK2_P set_property PACKAGE_PIN AW27 get_ports 250MHZ_CLK2_N set_property IOSTANDARD LVDS get_ports 250MHZ_CLK2_N set_property PACKAGE_PIN AM23 get_ports QSFP1_RECCLK_P set_property...

Page 118: ...1_DQ3 set_property PACKAGE_PIN H12 get_ports DDR4_C1_DQ4 set_property IOSTANDARD POD12_DCI get_ports DDR4_C1_DQ4 set_property PACKAGE_PIN G12 get_ports DDR4_C1_DQ5 set_property IOSTANDARD POD12_DCI ge...

Page 119: ...IOSTANDARD POD12_DCI get_ports DDR4_C1_DQ21 set_property PACKAGE_PIN H19 get_ports DDR4_C1_DQ22 set_property IOSTANDARD POD12_DCI get_ports DDR4_C1_DQ22 set_property PACKAGE_PIN H18 get_ports DDR4_C1_...

Page 120: ...IOSTANDARD POD12_DCI get_ports DDR4_C1_DQ40 set_property PACKAGE_PIN M23 get_ports DDR4_C1_DQ41 set_property IOSTANDARD POD12_DCI get_ports DDR4_C1_DQ41 set_property PACKAGE_PIN R21 get_ports DDR4_C1_...

Page 121: ...IOSTANDARD POD12_DCI get_ports DDR4_C1_DQ59 set_property PACKAGE_PIN F21 get_ports DDR4_C1_DQ60 set_property IOSTANDARD POD12_DCI get_ports DDR4_C1_DQ60 set_property PACKAGE_PIN E21 get_ports DDR4_C1_...

Page 122: ...set_property IOSTANDARD POD12_DCI get_ports DDR4_C1_DQ78 set_property PACKAGE_PIN A11 get_ports DDR4_C1_DQ79 set_property IOSTANDARD POD12_DCI get_ports DDR4_C1_DQ79 set_property PACKAGE_PIN D14 get_p...

Page 123: ...4_C1_BA0 set_property IOSTANDARD SSTL12_DCI get_ports DDR4_C1_BA0 set_property PACKAGE_PIN G13 get_ports DDR4_C1_BA1 set_property IOSTANDARD SSTL12_DCI get_ports DDR4_C1_BA1 set_property PACKAGE_PIN H...

Page 124: ...CI get_ports DDR4_C1_DQS3_C set_property PACKAGE_PIN F16 get_ports DDR4_C1_DQS3_T set_property IOSTANDARD DIFF_POD12_DCI get_ports DDR4_C1_DQS3_T set_property PACKAGE_PIN A18 get_ports DDR4_C1_DQS4_C...

Page 125: ...TL12_DCI get_ports DDR4_C1_ALERT_B set_property PACKAGE_PIN C8 get_ports DDR4_C1_ODT set_property IOSTANDARD SSTL12_DCI get_ports DDR4_C1_ODT set_property PACKAGE_PIN G10 get_ports DDR4_C1_PAR set_pro...

Page 126: ...E_PIN AW32 get_ports DDR4_C2_DQ13 set_property IOSTANDARD POD12_DCI get_ports DDR4_C2_DQ13 set_property PACKAGE_PIN AY32 get_ports DDR4_C2_DQ14 set_property IOSTANDARD POD12_DCI get_ports DDR4_C2_DQ14...

Page 127: ...ACKAGE_PIN BE34 get_ports DDR4_C2_DQ32 set_property IOSTANDARD POD12_DCI get_ports DDR4_C2_DQ32 set_property PACKAGE_PIN BF34 get_ports DDR4_C2_DQ33 set_property IOSTANDARD POD12_DCI get_ports DDR4_C2...

Page 128: ...ACKAGE_PIN BA40 get_ports DDR4_C2_DQ51 set_property IOSTANDARD POD12_DCI get_ports DDR4_C2_DQ51 set_property PACKAGE_PIN AW40 get_ports DDR4_C2_DQ52 set_property IOSTANDARD POD12_DCI get_ports DDR4_C2...

Page 129: ...PACKAGE_PIN BD25 get_ports DDR4_C2_DQ70 set_property IOSTANDARD POD12_DCI get_ports DDR4_C2_DQ70 set_property PACKAGE_PIN BD26 get_ports DDR4_C2_DQ71 set_property IOSTANDARD POD12_DCI get_ports DDR4_C...

Page 130: ...ts DDR4_C2_A9 set_property IOSTANDARD SSTL12_DCI get_ports DDR4_C2_A9 set_property PACKAGE_PIN AR28 get_ports DDR4_C2_A10 set_property IOSTANDARD SSTL12_DCI get_ports DDR4_C2_A10 set_property PACKAGE_...

Page 131: ...rty IOSTANDARD POD12_DCI get_ports DDR4_C2_DM8 set_property PACKAGE_PIN BA29 get_ports DDR4_C2_DM9 set_property IOSTANDARD POD12_DCI get_ports DDR4_C2_DM9 set_property PACKAGE_PIN BF31 get_ports DDR4_...

Page 132: ...et_property PACKAGE_PIN BE25 get_ports DDR4_C2_DQS8_T set_property IOSTANDARD DIFF_POD12_DCI get_ports DDR4_C2_DQS8_T set_property PACKAGE_PIN BB26 get_ports DDR4_C2_DQS9_C set_property IOSTANDARD DIF...

Page 133: ...3_72B_DQ5 set_property IOSTANDARD SSTL12 get_ports RLD3_C3_72B_DQ5 set_property PACKAGE_PIN K37 get_ports RLD3_C3_72B_DQ6 set_property IOSTANDARD SSTL12 get_ports RLD3_C3_72B_DQ6 set_property PACKAGE_...

Page 134: ...ARD SSTL12 get_ports RLD3_C3_72B_DQ23 set_property PACKAGE_PIN D40 get_ports RLD3_C3_72B_DQ24 set_property IOSTANDARD SSTL12 get_ports RLD3_C3_72B_DQ24 set_property PACKAGE_PIN C40 get_ports RLD3_C3_7...

Page 135: ...ARD SSTL12 get_ports RLD3_C3_72B_DQ42 set_property PACKAGE_PIN N27 get_ports RLD3_C3_72B_DQ43 set_property IOSTANDARD SSTL12 get_ports RLD3_C3_72B_DQ43 set_property PACKAGE_PIN P24 get_ports RLD3_C3_7...

Page 136: ...DARD SSTL12 get_ports RLD3_C3_72B_DQ61 set_property PACKAGE_PIN G25 get_ports RLD3_C3_72B_DQ62 set_property IOSTANDARD SSTL12 get_ports RLD3_C3_72B_DQ62 set_property PACKAGE_PIN B28 get_ports RLD3_C3_...

Page 137: ...SSTL12 get_ports RLD3_C3_72B_A8 set_property PACKAGE_PIN B32 get_ports RLD3_C3_72B_A9 set_property IOSTANDARD SSTL12 get_ports RLD3_C3_72B_A9 set_property PACKAGE_PIN B31 get_ports RLD3_C3_72B_A10 set...

Page 138: ...t_property PACKAGE_PIN B25 get_ports RLD3_C3_72B_DM3 set_property IOSTANDARD SSTL12 get_ports RLD3_C3_72B_DM3 set_property PACKAGE_PIN J31 get_ports RLD3_C3_72B_DK0_N set_property IOSTANDARD DIFF_SSTL...

Page 139: ...ARD DIFF_SSTL12 get_ports RLD3_C3_72B_QK4_P set_property PACKAGE_PIN M28 get_ports RLD3_C3_72B_QK5_N set_property IOSTANDARD DIFF_SSTL12 get_ports RLD3_C3_72B_QK5_N set_property PACKAGE_PIN M27 get_po...

Page 140: ...N11 BPI_FLASH_D1 Bank 0 D01_DIN_0 PACKAGE_PIN AM11 BPI_FLASH_D2 Bank 0 D02_0 PACKAGE_PIN AL11 BPI_FLASH_D3 Bank 0 D03_0 PACKAGE_PIN AJ11 BPI_FLASH_CE_B Bank 0 RDWR_FCS_B_0 set_property PACKAGE_PIN AM1...

Page 141: ...STANDARD LVCMOS18 get_ports BPI_FLASH_A4 set_property PACKAGE_PIN AU18 get_ports BPI_FLASH_A5 set_property IOSTANDARD LVCMOS18 get_ports BPI_FLASH_A5 set_property PACKAGE_PIN AV19 get_ports BPI_FLASH_...

Page 142: ...get_ports BPI_FLASH_A23 set_property IOSTANDARD LVCMOS18 get_ports BPI_FLASH_A23 set_property PACKAGE_PIN BE18 get_ports BPI_FLASH_A24 set_property IOSTANDARD LVCMOS18 get_ports BPI_FLASH_A24 set_prop...

Page 143: ...02_P set_property PACKAGE_PIN AT40 get_ports FMCP_HSPC_LA03_N set_property IOSTANDARD LVDS get_ports FMCP_HSPC_LA03_N set_property PACKAGE_PIN AT39 get_ports FMCP_HSPC_LA03_P set_property IOSTANDARD L...

Page 144: ...D LVDS get_ports FMCP_HSPC_LA12_N set_property PACKAGE_PIN AH33 get_ports FMCP_HSPC_LA12_P set_property IOSTANDARD LVDS get_ports FMCP_HSPC_LA12_P set_property PACKAGE_PIN AJ36 get_ports FMCP_HSPC_LA1...

Page 145: ...ty IOSTANDARD LVDS get_ports FMCP_HSPC_LA21_P set_property PACKAGE_PIN N35 get_ports FMCP_HSPC_LA22_N set_property IOSTANDARD LVDS get_ports FMCP_HSPC_LA22_N set_property PACKAGE_PIN N34 get_ports FMC...

Page 146: ...ts FMCP_HSPC_LA31_N set_property IOSTANDARD LVDS get_ports FMCP_HSPC_LA31_N set_property PACKAGE_PIN P37 get_ports FMCP_HSPC_LA31_P set_property IOSTANDARD LVDS get_ports FMCP_HSPC_LA31_P set_property...

Page 147: ...ANDARD LVDS get_ports FMCP_HSPC_HA06_N set_property PACKAGE_PIN V15 get_ports FMCP_HSPC_HA06_P set_property IOSTANDARD LVDS get_ports FMCP_HSPC_HA06_P set_property PACKAGE_PIN Y14 get_ports FMCP_HSPC_...

Page 148: ...LVDS get_ports FMCP_HSPC_HA15_P set_property PACKAGE_PIN R13 get_ports FMCP_HSPC_HA16_N set_property IOSTANDARD LVDS get_ports FMCP_HSPC_HA16_N set_property PACKAGE_PIN T14 get_ports FMCP_HSPC_HA16_P...

Page 149: ...operty IOSTANDARD LVDS get_ports FMCP_HSPC_REFCLK_C2M_P set_property PACKAGE_PIN AL34 get_ports FMCP_HSPC_REFCLK_M2C_N set_property IOSTANDARD LVDS get_ports FMCP_HSPC_REFCLK_M2C_N set_property PACKAG...

Page 150: ...MC_HPC1_LA00_CC_P set_property PACKAGE_PIN BB8 get_ports FMC_HPC1_LA01_CC_N set_property IOSTANDARD LVDS get_ports FMC_HPC1_LA01_CC_N set_property PACKAGE_PIN BB9 get_ports FMC_HPC1_LA01_CC_P set_prop...

Page 151: ...OSTANDARD LVDS get_ports FMC_HPC1_LA10_N set_property PACKAGE_PIN BB13 get_ports FMC_HPC1_LA10_P set_property IOSTANDARD LVDS get_ports FMC_HPC1_LA10_P set_property PACKAGE_PIN BA15 get_ports FMC_HPC1...

Page 152: ...roperty IOSTANDARD LVDS get_ports FMC_HPC1_LA19_P set_property PACKAGE_PIN AY10 get_ports FMC_HPC1_LA20_N set_property IOSTANDARD LVDS get_ports FMC_HPC1_LA20_N set_property PACKAGE_PIN AW11 get_ports...

Page 153: ...AGE_PIN AP15 get_ports FMC_HPC1_LA29_N set_property IOSTANDARD LVDS get_ports FMC_HPC1_LA29_N set_property PACKAGE_PIN AN15 get_ports FMC_HPC1_LA29_P set_property IOSTANDARD LVDS get_ports FMC_HPC1_LA...

Page 154: ..._property IOSTANDARD LVCMOS18 get_ports PHY1_PDWN_B_I_INT_B_O set_property PACKAGE_PIN BA21 get_ports PHY1_RESET_B set_property IOSTANDARD LVCMOS18 get_ports PHY1_RESET_B set_property PACKAGE_PIN AU22...

Page 155: ...S QSFP2 set_property PACKAGE_PIN AT21 get_ports QSFP2_INTL_LS set_property IOSTANDARD LVCMOS18 get_ports QSFP2_INTL_LS set_property PACKAGE_PIN AT24 get_ports QSFP2_LPMODE_LS set_property IOSTANDARD L...

Page 156: ...KAGE_PIN B17 get_ports GPIO_DIP_SW1 set_property IOSTANDARD LVCMOS12 get_ports GPIO_DIP_SW1 set_property PACKAGE_PIN G16 get_ports GPIO_DIP_SW2 set_property IOSTANDARD LVCMOS12 get_ports GPIO_DIP_SW2...

Page 157: ...KAGE_PIN BF22 get_ports GPIO_SW_W set_property IOSTANDARD LVCMOS18 get_ports GPIO_SW_W CPU RESET GPIO PB SWITCH set_property PACKAGE_PIN L19 get_ports CPU_RESET set_property IOSTANDARD LVCMOS12 get_po...

Page 158: ...ports PMOD1_5_LS set_property IOSTANDARD LVCMOS12 get_ports PMOD1_5_LS set_property PACKAGE_PIN M31 get_ports PMOD1_6_LS set_property IOSTANDARD LVCMOS12 get_ports PMOD1_6_LS set_property PACKAGE_PIN...

Page 159: ...rty IOSTANDARD LVCMOS18 get_ports PMBUS_ALERT_FPGA VADJ PGOOD set_property PACKAGE_PIN AK35 get_ports VADJ_1V8_PGOOD_LS set_property IOSTANDARD LVCMOS18 get_ports VADJ_1V8_PGOOD_LS FMC VADJ ON OFF set...

Page 160: ...ing the CE requirements for the PC Test Environment VCU118 Evaluation Kit Master Answer Record AR 68268 Declaration of Conformity The Virtex UltraScale VCU118 Declaration of Conformity is online Direc...

Page 161: ...quate measures Safety IEC 60950 1 2005 Information technology equipment Safety Part 1 General requirements EN 60950 1 2006 Information technology equipment Safety Part 1 General requirements Markings...

Page 162: ...oard and its documentation is available on the following websites VCU118 Evaluation Kit VCU118 Evaluation Kit Master Answer Record AR 68268 These Xilinx documents provide supplemental material useful...

Page 163: ...For additional documents associated with Xilinx devices design tools intellectual property boards and kits see the Xilinx documentation website The following websites provide supplemental material us...

Page 164: ...uffered as a result of any action brought by a third party even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same Xilinx assumes no obligation...

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