Xilinx VCU118, User Manual

Page: 42 / 164

VCU118 Board User Guide 42
UG1224 (v1.0) December 15, 2016 www.xilinx.com
Chapter 3: Board Component Descriptions
Table 3-7 lists the VCU118 clock sources to FPGA U1 connections.
QSFP2 Jitter attenuated clock U57
Silicon Labs Si5328B LVDS precision clock
multiplier/jitter attenuator. See Jitter Attenuated
Clock (SI5328_OUT2_P/N)
User SMA clock J34(P), J35(N)
User clock input SMAs. See User SMA Clock
(USER_SMA_CLOCK_P and USER_SMA_CLOCK_N).
QSFP clock 10 MHz-810 MHz U38
Silicon Labs Si570 3.3V LVDS I
2
C programmable
oscillator, 156.250 MHz default.
(QSFP_SI570_CLOCK_P/N)
Fixed 250 MHz U14/U21
Epson SG5032 3.3V LVDS I
2
C oscillator, fixed 250
MHz. U14 output drives U21 dual clock buffer.
(250MHZ_CLK1_P/N and 250MHZ_CLK2_P/N)
Table 3-6: VCU118 Board Clock Sources (Cont’d)
Clock Name Clock Ref. Des. Description
Table 3-7: VCU118 Clock Sources to XCVU9P FPGA U1 Connections
Clock Source
Device/U#.Pin#
Schematic Net Name I/O Standard FPGA (U1) Pin
SI53340/U157.9 SYSCLK1_300_P LVDS G31
SI53340/U157.10 SYSCLK1_300_N LVDS F31
SI5335A/U122.18 CLK_125MHZ_P LVDS AY24
SI5335A/U122.17 CLK_125MHZ_N LVDS AY23
SI5335A/U122.14 FPGA_EMCCLK
(2)
LVCMOS18 AL20
SI5335A/U122.10 SYSCTLR_CLK
(2)
LVCMOS18 U111.C7
SI53340/U104.9 USER_SI570_CLOCK_P LVDS H32
SI53340/U104.10 USER_SI570_CLOCK_N LVDS G32
SI53340/U157.13 USER_SI570_CLOCK1_P LVDS AW23
SI53340/U157.14 USER_SI570_CLOCK1_N LVDS AW22
SI53340/U104.11 MGT_SI570_CLOCK1_P NA
(2)
AJ9
SI53340/U104.12 MGT_SI570_CLOCK1_N NA
(2)
AJ8
SI53340/U104.13 MGT_SI570_CLOCK2_P NA
(2)
R9
SI53340/U104.14 MGT_SI570_CLOCK2_N NA
(2)
R8
SI53340/U104.15 MGT_SI570_CLOCK3_P NA
(2)
L9
SI53340/U104.16 MGT_SI570_CLOCK3_N NA
(2)
L8
SI5328B/U57.28 SI5328_OUT1_P NA
(1)
U9
SI5328B/U57.29 SI5328_OUT1_N NA
(1)
U8
SI5328B/U57.28 SI5328_OUT2_P NA
(1)
N9
SI5328B/U57.29 SI5328_OUT2_N NA
(1)
N8
SMA/J34.1 USER_SMA_CLOCK_P LVDS R32
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