![background image](http://html1.mh-extra.com/html/xilinx/kria-k26-som/kria-k26-som_design-manual_3372861023.webp)
Table 6: SOM240_2 Signal Pins (cont'd)
Pin Number
Signal Name
Signal Description
C32
HPC11_P
HPIO on bank 64
C33
HPC11_N
HPIO on bank 64
C34
GND
Ground
C35
HPC12_P
HPIO on bank 64
C36
HPC12_N
HPIO on bank 64
C37
GND
Ground
C38
HPC05_CC_P
HPIO clock-capable pin on bank 64
C39
HPC05_CC_N
HPIO clock-capable pin on bank 64
C40
GND
Ground
C41
HPC_CLK0_P
HPIO global clock pin on bank 64
C42
HPC_CLK0_N
HPIO global clock pin on bank 64
C43
GND
Ground
C44
VCCO_HPC
HPC I/O voltage rail, 1.0V to 1.8V
C45
GND
Ground
C46
HDB06
HDIO on bank 43
C47
HDB07
HDIO on bank 43
C48
HDB08_CC
HDIO clock-capable pin on bank 43
C49
GND
Ground
C50
HDB09
HDIO on bank 43
C51
HDB10
HDIO on bank 43
C52
HDB11
HDIO on bank 43
C53
GND
Ground
C54
HDC06
HDIO on bank 44
C55
HDC07
HDIO on bank 44
C56
HDC08_CC
HDIO clock-capable pin on bank 44
C57
GND
Ground
C58
HDC09
HDIO on bank 44
C59
HDC10
HDIO on bank 44
C60
HDC11
HDIO on bank 44
Connector Row D
D1
GTH_DP1_C2M_P
GTH Lane 1 RX
D2
GTH_DP1_C2M_N
GTH Lane 1 RX
D3
GND
Ground
D4
GND
Ground
D5
GTH_DP3_M2C_P
GTH Lane 3 TX
D6
GTH_DP3_M2C_N
GTH Lane 3 TX
D7
GND
Ground
D8
GND
Ground
D9
GTH_DP0_M2C_P
GTH Lane 0 TX
Chapter 2: Electrical Design Considerations
UG1091 (v1.0) April 20, 2021
Carrier Card Design for Kria SOM
23