Xilinx CAN FD v2.0 Product Manual Download Page 70

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CAN FD v2.0

PG223 December 5, 2018

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Chapter 3:

Designing with the Core

If you want to enable RX FIFO-1, you need to arrange the Filter Mask and ID register

as per the requirement. The

RXFP

field in RX FIFO Watermark register also needs to

be set accordingly to a value less than 'd31.

IMPORTANT:

Step #4 is only for Receive Mailbox mode.

4. Configure the Mask registers (MRB) for RX Mailbox buffers. Configure the RB-ID register

of the respective buffer and set the control bit in the RCS register to make the buffer

status Active.

5. Program the Interrupt Enable registers as per requirements.
6. Enable protocol controller by writing a 1 to the CEN bit in the SRR register.

After the occurrence of 11 consecutive recessive bits, the CAN FD clears the

CONFIG

bit

in the Status register to 0 and sets the appropriate Mode Status bit in the Status register.

RECOMMENDED:

If the CEN bit is cleared during core operation, Xilinx recommends resetting the core

so that operation starts afresh. Also, the LBACK, SLEEP, and SNOOP bits should never be set to 1 at the
same time.

Message Transmission, Cancellation, and Reception

Transmission

All messages written in the TX buffer must follow the required message format for the

DLC

, and

fields described earlier. Each

bit of the TX Buffer Ready Request (TRR)

TX – Host Actions

1. Poll the TRR register to check current pending transmission requests.
2. If all bits of the TRR register are set, a new transmission request can only be added if:

a. One or more buffer transmission requests are cancelled, or
b. One or more buffer transmissions complete.

3. If one or more bits of the TRR register are unset/clear, a new transmission request can be

added as follows:
a. First, prepare one or more message elements in the TX block RAM (by writing valid

DLC

, and

fields of each message element of the respective TX Buffer). If you

require event logging for this message element, set the

EFC

bit in the

DLC

field.

b. Enable interrupt generation as required.
c. Set corresponding

TRR

bit(s) to enable buffer ready requests. The Host can enable

many transmission requests in one write to the TRR register.

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Summary of Contents for CAN FD v2.0

Page 1: ...CAN FD v2 0 LogiCORE IP Product Guide Vivado Design Suite PG223 December 5 2018...

Page 2: ...source Utilization 9 Port Descriptions 9 Register Space 10 Chapter 3 Designing with the Core Operating Modes and States 63 Programming Model 68 Clocking 77 Resets 77 Interrupts 78 Chapter 4 Design Flo...

Page 3: ...x B Upgrading Upgrading in the Vivado Design Suite 90 Appendix C Debugging Finding Help on Xilinx com 91 Debug Tools 93 Hardware Debug 93 Interface Debug 94 Appendix D Additional Resources and Legal N...

Page 4: ...ast data rate IMPORTANT It is required to have a valid Bosch CAN FD protocol license before selling a device containing the Xilinx CAN FD IP core IP Facts LogiCORE IP Facts Table Core Specifics Suppor...

Page 5: ...d messages Supports transmit event FIFO Supports the following modes Disable Auto Retransmission DAR mode Snoop Bus Monitoring mode Sleep mode with Wake Up Interrupt Internal Loopback mode Bus Off Rec...

Page 6: ...levant CAN and CAN FD specifications is assumed Figure 1 1 illustrates the high level architecture of the CAN FD core and provides the interface connectivity Note The core requires an external PHY to...

Page 7: ...ement Module The TX Buffer Management Module TBMM interfaces with the CAN FD protocol engine to provide the next buffer to transmit on the CAN bus It manages the host access to the TX block RAM RX Buf...

Page 8: ...rwise generation halts with error License checkpoints are enforced by the following tools Vivado synthesis Vivado implementation write_bitstream Tcl command IMPORTANT IP license level is ignored at ch...

Page 9: ...nd Resource Utilization web page Port Descriptions The host interface of the CAN FD core is either the AXI4 Lite or the APB interface depending on the parameter selected in the Vivado IDE Table 2 1 de...

Page 10: ...can_clk_x2 Clock I This is fully synchronous to the CAN clock and is a multiple by 2 in frequency APB Interface Signals apb_clk Clock I APB clock apb_resetn Reset I Active Low synchronous reset apb_pw...

Page 11: ...Masks See Table 2 44 Table 2 3 CAN FD Core Register Address Map Start Address Name Access Description Notes 0x0000 SRR Read Write Software Reset Register Registers present in both RX Mailbox and RX S...

Page 12: ...therwise reserved 0x00B4 RCS1 Read Write See RX Buffer Control Status Register 0 0x00B8 RCS2 Read Write 0x00BC Reserved Reserved space Write has no effect Read always returns 0 0x00C0 IERBF0 Read Writ...

Page 13: ...BFL ERXFOFLW_1 ETXCRS ETXRRS ERXFWMFLL EWKUP ESLP EBSOFF EERROR RSVD ERXOFLW ETSCNT_OFLW ERXOK EBSFRD EPEE ETXOK EARBLST IER 0x0 0x0024 CTXEWMFLL CTXEOFLW RSVD CRXMNF CRXBOFLW CRXFWMFLL_1 CRXBFL CRXFO...

Page 14: ...B26 HCB25 HCB24 HCB23 HCB22 HCB21 HCB20 HCB19 HCB18 HCB17 HCB16 RCS1 0x0 0x00B8 CSB47 CSB46 CSB45 CSB44 CSB43 CSB42 CSB41 CSB40 CSB39 CSB38 CSB37 CSB36 CSB35 CSB34 CSB33 CSB32 HCB47 HCB46 HCB45 HCB44...

Page 15: ...ck mode If the SNOOP mode is set to 1 the core enters Snoop mode and does not participate in bus communication but only receives messages 0x00F8 RSVD Reserved 0x00FC RSVD Reserved Notes 1 These fields...

Page 16: ...t auto clears after node completes the Bus Off Recovery or leaves Bus Off state due to hard soft reset or CEN deassertion 5 DPEE R W 0 Disable Protocol Exception Event Detection Generation 1 Disable P...

Page 17: ...r counters are disabled and cleared to 0 Reads to the error counter register return zero 1 LBACK R W 0 Loopback Mode Select Request This is the Loopback mode request bit 1 Request core to be in Loopba...

Page 18: ...seen Note In SNOOP mode error counters are disabled and cleared to 0 Reads to the Error Counter register return 0 Table 2 8 Arbitration Phase Bit Register Bits Name Access Default Value Description 3...

Page 19: ...FD Data Phase 1 1 Indicates a bit error occurred in Data Phase Fast data rate 0 Indicates a bit error has not occurred in Data Phase Fast data rate after the last write to this bit If this bit is set...

Page 20: ...a stuff error has not occurred on the bus after the last write to this bit If this bit is set writing a 1 clears it 1 FMER 0 Form Error Indicates an error in one of the fixed form fields in the messag...

Page 21: ...ration State When this bit is set the BBSY and NORMAL status bits in this register do not mean anything 9 PEE_CONFIG R 0 PEE Mode Indicator 1 Indicates the core is in PEE mode Bus Integration State Wh...

Page 22: ...e is in Loopback mode 0 Indicates that the core is not in Loopback mode 0 CONFIG R 1 Configuration Mode Indicator Indicates that the core is in Configuration mode 1 Indicates that the core is in Confi...

Page 23: ...been lost due to buffer overflow condition Buffer index is captured in RXBOFLW_BI field This bit can be cleared by writing to the respective bit in the ICR RX FIFO 1 Watermark Full Interrupt Sequenti...

Page 24: ...n the ICR This bit is also cleared when a 0 is written to the CEN bit in the SRR 8 ERROR R 0 Error Interrupt 1 Indicates that an error occurred during message transmission or reception This bit can be...

Page 25: ...a 0 is written to the CEN bit in the SRR 0 ARBLST R 0 Arbitration Lost Interrupt 1 Indicates that arbitration was lost during message transmission This bit can be cleared by writing to the respective...

Page 26: ...t Enable 1 Enables interrupt generation if TXRRS bit in the ISR is set 0 Disables interrupt generation if TXRRS bit in the ISR is set 12 ERXFWMFLL R W 0 RX FIFO 0 Watermark Full Interrupt Enable Seque...

Page 27: ...rupt generation if TXOK bit in the ISR is set 0 Disables interrupt generation if TXOK bit in the ISR is set 0 EARBLOST R W 0 Arbitration Lost Interrupt Enable 1 Enables interrupt generation if ARBLST...

Page 28: ...ars the respective bit in the ISR Reads always 0 10 CSLP W 0 1 Clears Sleep interrupt status bit Writing a 1 to this bit clears the respective bit in the ISR Reads always 0 9 CBSOFF W 0 1 Clears Bus O...

Page 29: ...ost interrupt status bit Writing a 1 to this bit clears the respective bit in the ISR Reads always 0 Table 2 14 Interrupt Clear Register Cont d Bits Name Access Default Value Description Table 2 15 Ti...

Page 30: ...le of the data bit This bit can be written only when CEN bit in SRR is 0 7 0 DP_BRP 7 0 R W 0 Data Phase Baud Rate Prescaler These bits indicate the prescaler value for Data Bit Timing as specified in...

Page 31: ...7 R W Host writes 1 and core clears 0 TX Buffer_0 Ready Request This is control bit corresponds to TB0 message in TX block RAM Host writes 1 to indicate buffer is ready for transmission Core clears th...

Page 32: ...X Buffer_0 Cancel Request This is cancellation request bit corresponds to RR0 bit in TRR register Host writes 1 to indicate cancellation request of corresponding buffer ready request that is RR0 bit i...

Page 33: ...ISR does not set if CR0 bit in TCS register clears 6 ECRS6 5 ECRS5 4 ECRS4 3 ECRS3 2 ECRS2 1 ECRS1 0 ECRS0 Table 2 22 TX Event FIFO Status Register Bits Name Access Default Value Description 31 14 Res...

Page 34: ...ed if CEN bit is cleared RI gets reset to 0 if soft or hard reset is asserted Table 2 23 TX Event FIFO Watermark Register Bits Name Access Default Value Description 4 0 TXE_FWM R W 0xf TX Event FIFO F...

Page 35: ...ffer ID CSBx HCBx 11 Buffer is full it has received message CSBx HCBx 10 Buffer is invalid This condition can happen when core updates CS0 bit to indicate Buffer is full and at the same time Host trie...

Page 36: ...16 ERBF31 ERBF16 R W 0 Note These bits exist based on the number of RX buffers 15 ERBF15 R W 0 RX Buffer_15 1 Full Interrupt Enable Description same as ERBF0 RX Buffer_0 Full Interrupt Enable is for...

Page 37: ...If the UAF bits are changed from a 1 to 0 during reception of a message then that message might or might not be stored 0 ERBF32 R W 0 RX Buffer_32 Full Interrupt Enable 1 Enables setting RXBFL bit in...

Page 38: ...eptance Filter Mask Pair 18 Description same as UAF0 17 UAF17 R W 0 Use Acceptance Filter Mask Pair 17 Description same as UAF0 16 UAF16 R W 0 Use Acceptance Filter Mask Pair 16 Description same as UA...

Page 39: ...Indicates Acceptance Filter Mask register 0 AFMR0 or M0 and Acceptance Filter ID register 0 AFID0 or F0 pair is used for acceptance filtering 0 Indicates AFMR0 and AFID0 pair is not used for acceptan...

Page 40: ...ts from location 0x4100 RI 0x1 Next message read starts from location 0x4148 RI is maintained if CEN bit is cleared RI gets reset to 0 if soft or hard reset is asserted 15 Reserved 0 Reserved 14 8 FL...

Page 41: ...ption 31 21 Reserved 0 Reserved 20 16 RXFP R W 0x1f Receive Filter Partition Received messages which match Filter Mask pairs from 0 to RXFP are stored in RX FIFO 0 Received messages which match Filter...

Page 42: ...art Address Name Access Description Notes 0x0100 TB0 ID Read Write TB ID Register TB0 Message space inside memory mapped TX block RAM Only required DW locations needs to be written as per FDF and DLC...

Page 43: ...d Write TB8 to TB15 Message Space 0x0340 0x0384 TB8 Read Write Reserved if number of TX buffers 8 In this case core does not allow any write access to this address space and read access returns 0 0x03...

Page 44: ...0x07BC TB23 Read Write 0x07C0 0x0804 TB24 Read Write 0x0808 0x084C TB25 Read Write 0x0850 0x0894 TB26 Read Write 0x0898 0x08DC TB27 Read Write Reserved if number of TX buffers 8 or 16 In this case co...

Page 45: ...its indicate the Standard Frame ID This field is valid for both CAN and CAN FD Standard and Extended Frames 20 SRR RTR RRS Control N A Substitute Remote Transmission Request For Extended CAN frames an...

Page 46: ...me Control Status Default Value Description 31 28 DLC 3 0 Control N A Data Length Code This is the data length code of the control field of the CAN and CAN FD frame 27 EDL FDF Control N A Extended Dat...

Page 47: ...eeds to be transmitted with CAN or CAN FD frame based on the DLC control field 23 16 Data bytes1 7 0 N A Data Byte 1 Data byte needs to be transmitted with CAN or CAN FD frame based on the DLC control...

Page 48: ...and CAN FD Standard and Extended Frames 20 SRR RTR RRS Status N A Substitute Remote Transmission Request For Extended CAN frames and Extended CAN FD frame this bit is transmitted at SRR position of t...

Page 49: ...here are no CAN FD remote frames Table 2 36 TXE FIFO TB DLC Register Bits Name Control Status Default Value Description 31 28 DLC Status N A Data Length Code This is the data length code of the contro...

Page 50: ...core for status purpose for successfully transmitted message Table 2 37 CAN FD RX Message Space Sequential FIFO Buffers RX FIFO 0 Start Address Name Access Description Notes 64 Message Deep Sequentia...

Page 51: ...B0 DW8 Read Only 0x212C RB0 DW9 Read Only 0x2130 RB0 DW10 Read Only 0x2134 RB0 DW11 Read Only 0x2138 RB0 DW12 Read Only 0x213C RB0 DW13 Read Only 0x2140 RB0 DW14 Read Only 0x2144 RB0 DW15 Read Only RB...

Page 52: ...n message IMPORTANT Ensure no unintended writes are done from Host interface to RX block RAM message space core does not block writes to RX block RAM message space 0x4104 RB0_1 DLC Read Only RB DLC Re...

Page 53: ...18 Status N A Standard Message ID The Identifier portion for a Standard Frame is 11 bits These bits indicate the Standard Frame ID This field is valid for both CAN and CAN FD Standard and Extended Fra...

Page 54: ...Transmission Request This bit differentiates between CAN extended data frames and CAN extended remote frames 1 Indicates the received message is a CAN Remote Frame 0 Indicates the received message is...

Page 55: ...as no meaning if the received frame is a CAN frame 24 21 Reserved N A N A Reserved Read from this field return 0 20 16 Matched_Filter _Index 4 0 Status N A This status field is written by the core in...

Page 56: ...are equal the message is stored in RX FIFO 0 5 Acceptance filtering is processed by each of the defined filters If the incoming identifier passes through any acceptance filter the message is stored i...

Page 57: ...0 is full the message is dropped irrespective of RX FIFO 1 status and RX FIFO 0 overflow is indicated Similarly if the incoming message fulfills condition 5 and RX FIFO 1 is full the message is droppe...

Page 58: ...fier stored in the acceptance filter ID register The mask bits define which identifier bits stored in the Acceptance Filter ID register are compared to the incoming message identifier for CAN or CAN F...

Page 59: ...0 Identifier Extension Mask Used for masking the IDE bit 1 Indicates the corresponding bit in Acceptance Mask ID register is used when comparing the incoming message identifier 0 Indicates the corres...

Page 60: ...xtended frames Table 2 44 CAN FD RX Message Space Mailbox Buffers Start Address Name Access Description Notes Mailbox Buffer Space 0x2100 RB0 ID Read Write See RB ID Register Only required DW location...

Page 61: ...es not allow any write access to this address space and read access returns 0 0x25C8 0x260C RB17 Read Write 0x29B8 0x29FC RB31 Read Write RB32 to RB47 Message Space 0x2A00 0x2A44 RB32 Read Write Reser...

Page 62: ...te access outside the respective address space and read access returns 0 0x2F04 MRB1 Read Write See Acceptance Filter Mask Register Mask for mailbox buffer RB1 0x2F08 MRB2 Read Write See Acceptance Fi...

Page 63: ...e designing with the core Operating Modes and States The CAN FD core supports the following modes and states Configuration Normal Loopback Sleep Snoop Protocol Exception PEE state Bus Off Recovery Sta...

Page 64: ...uration mode after detecting 11 consecutive recessive bits on the CAN bus Core Operating Modes X14812 081518 Table 3 1 CAN FD Core Operating Mode Transitions System Hard Reset SRR Register Bits MSR Re...

Page 65: ...es not mean anything 2 Transition to Bus Off state depends on Transmit Error Count value as per standard specification Recovery from Bus Off state depends on SBR and ABR bit settings in the MSR regist...

Page 66: ...when normal operation is resumed Message cancellation is permitted New messages can be added for transmission provided the SNOOP bit is not set in the MSR register If there are new received messages...

Page 67: ...rs or sequential FIFO buffers in Loopback mode It does not participate in normal bus communication and does not receive any messages transmitted by other CAN nodes the external TX line is ignored It d...

Page 68: ...in the CAN FD frame provided the DPEE bit is not set in the MSR register It comes out of this state after detecting a sequence of 11 nominal recessive bits on the CAN bus and as per protocol specific...

Page 69: ...hase sample point position Program the Arbitration Phase Nominal Baud Rate Prescaler register and Arbitration Phase Nominal Bit Timing register with the value calculated for the particular arbitration...

Page 70: ...BACK SLEEP and SNOOP bits should never be set to 1 at the same time Message Transmission Cancellation and Reception Transmission All messages written in the TX buffer must follow the required message...

Page 71: ...ccessful transmission on the CAN bus or due to Cancellation or due to DAR based transmission 4 If enabled through the IETRS and IER the TXRRS bit is set in the ISR register and interrupt is generated...

Page 72: ...r the transmission succeeds or fails arbitration loss or error b When the core is performing a scheduling round to find out the next buffer for transmission In this case cancellation is performed afte...

Page 73: ...pair a has corresponding UAF bit to control enable disable Filtering when RX FIFO 1 is absent or disabled Filtering is performed in the following sequence 1 The incoming Identifier is masked with the...

Page 74: ...n any RX FIFO a Filter pair registers are stored in the block RAM memory Host has to ensure each used filter pair is properly initialized Asserting a software reset or system reset does not clear thes...

Page 75: ...back to Active if you wish to continue with the same ID Mask or Inactive if you wish to reprogram the ID Mask Note The CAN FD can read the ID field of the Full buffer for the current match process so...

Page 76: ...k RAM asserting a software reset or system reset does not clear these register contents Host has to properly initialize them before use Notes on the ID Match Process 1 It is expected that the AXI4 Lit...

Page 77: ...can be 8 to 200 MHz The core has another clock can_clk_x2 which is fully synchronous to can_clk and is a multiple by two of can_clk in frequency The can_clk_x2 clock is used to drive two CAN interface...

Page 78: ...ng AXI4 Lite APB transaction might terminate abruptly In general the system reset pulse should be greater than at least two CAN clock cycles IMPORTANT Because the Transfer layer is reset asynchronousl...

Page 79: ...r ICR Two conditions cause the interrupt line to be asserted If a bit in the ISR is 1 and the corresponding bit in the IER is 1 Changing an IER bit from a 0 to 1 when the corresponding bit in the ISR...

Page 80: ...ivado Design Suite If you are customizing and generating the core in the IP integrator see the Vivado Design Suite User Guide Designing IP Subsystems using IP Integrator UG994 Ref 8 for detailed infor...

Page 81: ...name must begin with a letter and be composed of the following characters a to z A to Z 0 to 9 and _ Processor Interface This parameter determines if the AXI4 Lite or APB interface is used to communi...

Page 82: ...is parameter determines if the IP has a second RX FIFO It is valid and applicable only when the selected RX Mode is Sequential RX FIFO 1 Depth This parameter defines the depth of RX Buffer FIFO 1 It i...

Page 83: ...CAN clock and AXI4 clock can be asynchronous or clocked from the same source When both clocks are asynchronous to each other the AXI4 clock is required to run at a higher frequency The CAN clock freq...

Page 84: ...ction is not applicable for this IP core Simulation For comprehensive information about Vivado simulation components as well as information about using supported third party tools see the Vivado Desig...

Page 85: ...erator and checker modules This example design includes the following modules Clock Generator The clocking wizard is used to generate two clocks one for the register interface AXI4 Lite and the other...

Page 86: ...t Completed Successfully If the test fails the following message is displayed ERROR Test Failed If the test hangs the following message is displayed ERROR Test did not complete timed out Example Seque...

Page 87: ...r Partner to receive two packets and compares data for correct reception DUT packets are of higher priority than Partner Waits for DUT to receive two packets If DUT is configured in FIFO mode the pack...

Page 88: ...Suite Figure 6 1 shows the test bench for the CAN FD example design The top level test bench generates a 200 MHz clock and drives an initial reset to the example design X Ref Target Figure 6 1 Figure...

Page 89: ...e programmed to have the following a Same Arbitration Phase bit rate b Same Data Phase bit rate c Same Arbitration Phase Sample Point Position d Same Data Phase Sample Point Position Requirements c an...

Page 90: ...IFO 1 Depth parameters define the depths of RX Buffer FIFO 0 and RX Buffer FIFO 1 respectively Port Changes See Table B 1 for a list of new and changed ports in v2 0 Table B 1 New Ports Port Name Note...

Page 91: ...her product support Documentation This product guide is the main document associated with the CAN FD This guide along with documentation related to all products that aid in the design process can be f...

Page 92: ...s Master Answer Record for the CAN FD AR 65142 Technical Support Xilinx provides technical support at the Xilinx Support web page for this LogiCORE IP product when used as described in the product doc...

Page 93: ...ons VIO 2 0 and later versions See the Vivado Design Suite User Guide Programming and Debugging UG908 Ref 12 Hardware Debug These are some common issues that might be encountered 1 The desired baud ra...

Page 94: ...N FD protocol and other recommendations see the standard specification and other white paper references in the References page 97 If any of the listed requirements are not met various frame errors can...

Page 95: ...e met The s_axi_aclk and can_clk inputs are connected and toggling The interface is not being held in reset and s_axi_areset is an active Low reset The interface is enabled and s_axi_aclken is active...

Page 96: ...filter and search to find information To open the Xilinx Documentation Navigator DocNav From the Vivado IDE select Help Documentation and Tutorials On Windows select Start All Programs Xilinx Design T...

Page 97: ...ate Specification version v1 0 Robert Bosch GmbH 4 CAN version 2 0A and B Specification Robert Bosch GmbH 5 Mutter Dr Arthur Robustness of a CAN FD Bus System About Oscillator Tolerance and Edge Devia...

Page 98: ...ty and support terms contained in a license issued to you by Xilinx Xilinx products are not designed or intended to be fail safe or for use in any application requiring fail safe performance you assum...

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