CAN FD v2.0
34
PG223 December 5, 2018
Chapter 2:
Product Specification
TX Event FIFO Watermark Register (Address 0x00A4)
6:5
Reserved
-
0
Reserved
4:0
TXE_RI[4:0]
R
0
Read Index (0 to 31)
Each time IRI bit is set, core increments read index
by + 1 (provided FILL level is not 0) and maintains
it for Host to access next available message.
RI = 0x0 -> Next message read starts from location
= 0x2000
RI = 0x1 -> Next message read starts from location
= 0x2008
RI is maintained if CEN bit is cleared.
RI gets reset to 0 if soft or hard reset is asserted.
Table 2-23:
TX Event FIFO Watermark Register
Bits
Name
Access
Default
Value
Description
4:0
TXE_FWM
R/W
0xf
TX Event FIFO Full Watermark
TX Event FIFO generates FULL interrupt based on
the value programmed in this field.
Set it within (1-31) range.
The TX FIFO Full Watermark interrupt in the ISR
register continues to assert as long as the TX Event
FIFO Fill Level is above TX Event FIFO Full
watermark.
This field can be written to only when CEN bit in
SRR is 0.
31:5
Reserved
-
0
Reserved.
Table 2-22:
TX Event FIFO Status Register
(Cont’d)
Bits
Name
Access Default
Value
Description
