Xilinx CAN FD v2.0, Product Manual

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CAN FD v2.0 27
PG223 December 5, 2018 www.xilinx.com
Chapter 2: Product Specification
Interrupt Clear Register (Address 0x0024)
The Interrupt Clear register (ICR) is used to clear interrupt status bits in the ISR register.
5 ETSCNT_OFLW R/W 0
Timestamp Counter Overflow Interrupt Enable.
• 1 = Enables interrupt generation if TSCNT_OFLW bit in the ISR is set.
• 0 = Disables interrupt generation if TSCNT_OFLW bit in the ISR is set.
4 ERXOK R/W 0
New Message Received Interrupt Enable.
• 1 = Enables interrupt generation if RXOK bit in the ISR is set.
• 0 = Disables interrupt generation if RXOK bit in the ISR is set.
3 EBSFRD R/W 0
Bus-Off Recovery Done Interrupt Enable.
• 1 = Enables interrupt generation if BSFRD bit in the ISR is set.
• 0 = Disables interrupt generation if BSFRD bit in the ISR is set.
2 EPEE R/W 0
Protocol Exception Event Interrupt Enable.
• 1 = Enables interrupt generation if PEE bit in the ISR is set.
• 0 = Disables interrupt generation if PEE bit in the ISR is set.
1 ETXOK R/W 0
Transmission Successful Interrupt Enable.
• 1 = Enables interrupt generation if TXOK bit in the ISR is set.
• 0 = Disables interrupt generation if TXOK bit in the ISR is set.
0 EARBLOST R/W 0
Arbitration Lost Interrupt Enable
• 1 = Enables interrupt generation if ARBLST bit in the ISR is set.
• 0 = Disables interrupt generation if ARBLST bit in the ISR is set.
Table 2-13: Interrupt Enable Register (Cont’d)
Bits Name Access Default
Value
Description
Table 2-14: Interrupt Clear Register
Bits Name Access
Default
Value
Description
31 CTXEWMFLL W 0
• 1 = Clears TX Event FIFO Watermark Full interrupt status bit.
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
30 CTXEOFLW W 0
• 1 = Clears TX Event FIFO Overflow interrupt status bit.
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
17 CRXMNF W 0
• 1 = Clears RX Match Not Finished interrupt status bit.
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
16
CRXBOFLW/
CRXFWMFLL_1
W 0
• 1 = Clears RX Buffer Overflow interrupt status bit (Mailbox mode).
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
• 1 = Clears RX FIFO-1 Watermark Full interrupt status bit
(Sequential/FIFO Mode).
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
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