Xilinx CAN FD v2.0, Product Manual

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CAN FD v2.0 42
PG223 December 5, 2018 www.xilinx.com
Chapter 2: Product Specification
CAN FD TX Message Space Register Descriptions
5:0 RXFWM R/W 0xf
RX FIFO-0 Full Watermark.
RX FIFO-0 generates FULL interrupt based on the value
programmed in this field.
Set it within (1-63) range.
The RX FIFO-0 Full Watermark interrupt in the ISR register
continues to assert as long as the RX FIFO-0 Fill Level is above
RX FIFO-0 Full watermark.
This field can be written to only when CEN bit in SRR is 0.
Notes:
1. This register space is reserved for RX Mailbox buffer mode. Write has no effect and read returns 0.
Table 2-30: CAN FD TX Message Space
Start
Address
Name Access Description Notes
0x0100 TB0-ID Read, Write
TB ID Register
TB0 Message space inside
memory mapped TX block
RAM.
Only required DW locations
needs to be written as per
FDF and DLC field for a given
message.
0x0104 TB0-DLC Read, Write TB DLC Register
0x0108 TB0-DW0 Read, Write TB DW0 Register
0x010C TB0-DW1 Read, Write
See TB DW0 Register
0x0110 TB0-DW2 Read, Write
0x0114 TB0-DW3 Read, Write
0x0118 TB0-DW4 Read, Write
0x011C TB0-DW5 Read, Write
0x0120 TB0-DW6 Read, Write
0x0124 TB0-DW7 Read, Write
0x0128 TB0-DW8 Read, Write
0x012C TB0-DW9 Read, Write
0x0130 TB0-DW10 Read, Write
0x0134 TB0-DW11 Read, Write
0x0138 TB0-DW12 Read, Write
0x013C TB0-DW13 Read, Write
0x0140 TB0-DW14 Read, Write
0x0144 TB0-DW15 Read, Write
Table 2-29: RX FIFO Watermark Register (Cont’d)
Bits Name Access Default
Value
Description
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