JODY-W2 - System integration manual
UBX-18068879 - R14
System description
Page 16 of 84
C1 - Public
Name
Pin
Description
Internal PU/PD
LTE_COEX_TX 13
Shall be set high during reset
Weak PU
BT_UART_TX 36
Shall be set low during reset
A 51 k
Ω
pull-down resistor is implemented on the module.
Table 8: Additional configuration pins
1.4
Data communication interfaces
JODY-W2 series modules use SDIO 3.0 and high-speed UART as host interface. The Wi-Fi traffic is
always communicated through the SDIO host interface. Depending on the configuration, the
high-speed UART interface can be configured for the Bluetooth/Bluetooth LE traffic between the host
and the JODY-W2 module series.
⚠
Use of the high-speed UART interface is only possible with the SDIO-UART software package. The
SDIO-SDIO software package supports only the SDIO host interface.
SDIO 3.0 interface
JODY-W2 series modules include a SDIO device interface compatible with the industry standard SDIO
3.0 specification (UHS-I, up to 104 Mbyte/s) and allows a host controller using the SDIO bus protocol
to access Wi-Fi and Bluetooth functions. The modules also support legacy modes, such as default
speed and High-Speed modes.
☞
The SDIO signal voltage is fixed to 1.8 V for Default Speed and High-Speed modes.
A module acts as a device on the SDIO bus.
summarizes the bus speed modes supported by
the module.
Bus Speed Mode
Max. Bus Speed [MB/s]
Max. Clock Frequency [MHz]
Signal Voltage (1V8) [V]
SDR104
104
208
1.8
SDR50
50
100
1.8
DDR50
50
50
1.8
SDR25
25
50
1.8
SDR12
12.5
25
1.8
High Speed
25
50
Only supported at 1.8 V
Default Speed
12.5
25
Only supported at 1.8 V
Table 9: SDIO supported rates for JODY-W2
Pull-up resistors are required for all SDIO data and command lines. These pull-up resistors can be
provided either externally on the host PCB or internally in the host application processor. JODY-W2
includes programmable internal PU/PD. Depending on the routing of the SDIO lines on the host,
termination resistors in series to the traces might also be needed. This to improve signal integrity or
reduce EMC radiation. See also
Name
I/O
Description
Remarks
SD_CLK
I
SDIO Clock input
SD_CMD
I/O
SDIO Command line
Pull-up resistors are required
SD_D0
I/O
SDIO Data line bit [0]
Pull-up resistors are required
SD_D1
I/O
SDIO Data line bit [1]
Pull-up resistors are required
SD_D2
I/O
SDIO Data line bit [2]
Pull-up resistors are required
SD_D3
I/O
SDIO Data line bit [3]
Pull-up resistors are required
Table 10: SDIO signal definition
The SDIO host interface pins of the module are powered by the
1V8
voltage domain.
