u-blox JODY-W2, System Integration Manual

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JODY-W2 - System integration manual
UBX-18068879 - R14 System description Page 15 of 84
C1 - Public
Figure 5: Power-down sequence of JODY-W2 module
Wake-up signals
JODY-W2 provides module-to-host, wake-up signals that are used to exit the host from any sleep
mode over Wi-Fi or Bluetooth. The wake-up signals are powered by the
VIO voltage domain.
Name Module pin Chipset GPIO Description
HOST_WAKE 10 GPIO_1 Wi-Fi to host out-of-band wake-up signal (output)
GPIO_20 12 GPIO_20 Bluetooth to host out-of-band wake-up signal (output)
PCM_IN 18 GPIO_4 Alternative Bluetooth to out-of-band wake-up signal if PCM is not
used (output)
Table 6: Wake-up signal definition
Configuration pins
Two dedicated boot-strap configuration pins ( CONFIG[0] , CONFIG[1] ) determine the configuration of
the host interface after system reset. Additional multiplexed pins ( PCM_OUT , LTE_COEX_TX ,
BT_UART_TX , BT_UART_RTS ) are used as configuration inputs following a reset and revert to their
normal function immediately after system reset.
By default, the configuration pins are high at logic level 1, unless otherwise noted. A 100 k
Ω
pull down
resistor to ground is required to set the pins low. No external circuitry is required to set a configuration
pin to a high level.
Table 7 describes the boot-strap configuration options that are set by CONFIG[0] and CONFIG[1] pins
and used to configure the host communication interfaces:
• SDIO-UART: Wi-Fi commands and data are transferred through the SDIO bus to the module. The
high-speed UART interface is used for Bluetooth communication.
• SDIO-SDIO: Wi-Fi and Bluetooth communication are transferred through the SDIO interface.
CONFIG[1] CONFIG[0] Wi-Fi Bluetooth Firmware download Number of SDIO functions
1 0 SDIO UART SDIO+UART (parallel/Serial) 1 (Wi-Fi)
1 1 SDIO SDIO SDIO+SDIO (parallel/Serial) 2 (Wi-Fi, Bluetooth)
Table 7: Host interface configuration options
Additional configuration pins must be set to their pre-requisite states following a reset as shown in
Table 8. The Internal PU/PD sets the default logic level if the pin is not connected to any external
component.
Name Pin Description Internal PU/PD
PCM_OUT 17 Shall be set high during reset Weak PU
BT_UART_RTS 38 Shall be set high during reset Weak PU