u-blox JODY-W2, System Integration Manual

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JODY-W2 - System integration manual
UBX-18068879 - R14 Design-in Page 29 of 84
C1 - Public
JODY-W2 series supports a 1.8 V SDIO interface only. A level shifter is needed to connect to a 3.3 V
host CPU. An implementation of a level shifter is described in the JODY-W2 level shifter application
note
[12] . Further information about how to connect the SDIO interface on the EVK is described in
EVK-JODY-W2 user guide [13] .
High-speed UART interface
The high-speed UART interface for the JODY-W2 complies with the HCI UART Transport layer and
uses the settings according to
Table 20 .
UART Settings
baud rate default 3000000 Baud
Data bits 8
Parity bit No parity
Stop bit 1 stop bit
Flow Control RTS/CTS
Table 20: HCI UART Transport layer settings
Flow control with RTS/CTS is used to prevent temporary UART buffer overrun. It should not be used
for flow control of HCI as HCI has its own flow control mechanisms for HCI commands, HCI events and
HCI data.
• If CTS is 1, then the Host/Host Controller can send.
• If CTS is 0, then the Host/Host Controller is not allowed to send.
☞
It is mandatory to use the hardware flow control. Otherwise, JODY-W2 does not answer.
Baud rates
1200 38400 460800 1500000 3000000 (default)
2400 57600 500000 1843200 3250000
4800 76800 921600 2000000 3692300
9600 115200 1000000 2100000 4000000
19200 230400 1382400 2764800
Table 21: Possible baud rates for the UART interface
After loading the firmware, the baud rate is set to 3000000 baud. A host application can configure
any desired baud shown in
Table 21 using the dedicated HCI command:
HCI_CMD_MARVELL_UART_BAUD
The command is generated completely at the old baud rate. Once the host receives the command at
the old baud rate, it can switch to the new baud rate and should wait for 5 ms or more before sending
the new command.
2.5 Other interfaces and notes
All pins have internal keeper resistors; leave it open if not used.
2.6 General high-speed layout guidelines
These general design guidelines are considered as best practices and are valid for any bus present in
the JODY-W2 modules; the designer should prioritize the layout of higher speed busses. Low
frequency signals are generally not critical for layout.
hcitool – i hci0 cmd 0x3F 0x0009 <4 byte value for baudrate>